mirror of git://gcc.gnu.org/git/gcc.git
Rename attributes and add Float16 shift left.
2025-10-06 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/float16.md (fp16_float_convert): Rename from FP16_CONVERT. (fp16_binary_op): Rename from FP16_BINARY. (fp16_binary_name): Rename from FP16_BINARY_NAME. (UNSPEC_FP16_SHIFT_LEFT_32BIT): Rename from UNSPEC_V8BF_SHIFT_LEFT_32BIT. (<fp16_vector8>_shift_left_32bit): Rename from v8bf_shift_left_32bit and add support for HFmode. (extend<FP16_HW:mode><fp16_float_convert:mode>2): Rename from extend<FP16_HW:mode><FP16_CONVERT:mode>2. (trunc<fp16_float_convert:mode><FP16_HW:mode>2): Rename from trunc<FP16_CONVERT:mode><FP16_HW:mode>2. (*cvt_fp16_to_v4sf_<mode>_le): Rename cvt_fp16_to_v4sf_insn from CVT_FP16_TO_V4SF_INSN. (cvt_fp16_to_v4sf_<mode>_b): Likewise. (<fp16_binary_name>bf3): Rename from <FP16_BINARY_NAME>bf3.
This commit is contained in:
Michael Meissner
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fb9549791f
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887e402b28
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@ -38,15 +38,15 @@
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;; Mode iterator for floating point modes other than SF/DFmode that we
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;; convert to/from _Float16 (HFmode) via DFmode.
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(define_mode_iterator FP16_CONVERT [TF KF IF SD DD TD])
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(define_mode_iterator fp16_float_convert [TF KF IF SD DD TD])
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;; Code iterator giving the basic operations for bfloat16 floating point
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;; operations.
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(define_code_iterator FP16_BINARY [plus div minus mult smax smin])
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(define_code_iterator fp16_binary_op [plus div minus mult smax smin])
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;; Code attribute that gives the standard name for the bfloat16
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;; operations done via V4SF vector.
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(define_code_attr FP16_BINARY_NAME [(plus "add")
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(define_code_attr fp16_binary_name [(plus "add")
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(div "div")
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(minus "sub")
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(mult "mul")
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@ -55,7 +55,7 @@
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;; Mode attribute giving the instruction to convert the even
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;; V8HFmode or V8BFmode elements to V4SFmode
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(define_mode_attr CVT_FP16_TO_V4SF_INSN [(BF "xvcvbf16spn")
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(define_mode_attr cvt_fp16_to_v4sf_insn [(BF "xvcvbf16spn")
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(HF "xvcvhpsp")
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(V8BF "xvcvbf16spn")
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(V8HF "xvcvhpsp")])
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@ -77,7 +77,7 @@
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;; UNSPEC constants
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(define_c_enum "unspec"
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[UNSPEC_V8BF_SHIFT_LEFT_32BIT
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[UNSPEC_FP16_SHIFT_LEFT_32BIT
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UNSPEC_CVT_FP16_TO_V4SF
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UNSPEC_XXSPLTW_FP16
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UNSPEC_XVCVSPBF16_BF])
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@ -202,13 +202,14 @@
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[(set_attr "type" "fpsimple")
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(set_attr "length" "12")])
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;; Vector shift left by 32 bits to get the bfloat16 value into the
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;; upper 32 bits for the conversion.
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(define_insn "v8bf_shift_left_32bit"
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[(set (match_operand:V8BF 0 "register_operand" "=wa")
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(unspec:V8BF [(match_operand:BF 1 "register_operand" "wa")]
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UNSPEC_V8BF_SHIFT_LEFT_32BIT))]
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"TARGET_BFLOAT16_HW"
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;; Vector shift left by 32 bits to get the 16-bit floating point value
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;; into the upper 32 bits for the conversion.
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(define_insn "<fp16_vector8>_shift_left_32bit"
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[(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa")
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(unspec:<FP16_VECTOR8>
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[(match_operand:FP16_HW 1 "vsx_register_operand" "wa")]
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UNSPEC_FP16_SHIFT_LEFT_32BIT))]
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""
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"xxsldwi %x0,%x1,%x1,1"
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[(set_attr "type" "vecperm")])
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@ -245,9 +246,9 @@
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;; Use DFmode to convert to/from 16-bit floating point types for
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;; scalar floating point types other than SF/DFmode.
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(define_expand "extend<FP16_HW:mode><FP16_CONVERT:mode>2"
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[(set (match_operand:FP16_CONVERT 0 "vsx_register_operand")
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(float_extend:FP16_CONVERT
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(define_expand "extend<FP16_HW:mode><fp16_float_convert:mode>2"
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[(set (match_operand:fp16_float_convert 0 "vsx_register_operand")
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(float_extend:fp16_float_convert
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(match_operand:FP16_HW 1 "vsx_register_operand")))]
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""
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{
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@ -261,10 +262,10 @@
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DONE;
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})
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(define_expand "trunc<FP16_CONVERT:mode><FP16_HW:mode>2"
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(define_expand "trunc<fp16_float_convert:mode><FP16_HW:mode>2"
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[(set (match_operand:FP16_HW 0 "vsx_register_operand")
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(float_truncate:FP16_HW
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(match_operand:FP16_CONVERT 1 "vsx_register_operand")))]
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(match_operand:fp16_float_convert 1 "vsx_register_operand")))]
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""
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{
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rtx df_tmp = gen_reg_rtx (DFmode);
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@ -359,7 +360,7 @@
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(const_int 5)
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(const_int 7)]))))]
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"!WORDS_BIG_ENDIAN"
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"<CVT_FP16_TO_V4SF_INSN> %x0,%x1"
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"<cvt_fp16_to_v4sf_insn> %x0,%x1"
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[(set_attr "type" "vecfloat")])
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(define_insn "*cvt_fp16_to_v4sf_<mode>_be"
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@ -372,7 +373,7 @@
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(const_int 4)
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(const_int 6)]))))]
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"WORDS_BIG_ENDIAN"
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"<CVT_FP16_TO_V4SF_INSN> %x0,%x1"
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"<cvt_fp16_to_v4sf_insn> %x0,%x1"
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[(set_attr "type" "vecfloat")])
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;; Duplicate and convert a 16-bit floating point scalar to V4SFmode.
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@ -408,9 +409,9 @@
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;; be 0, so we use a splat operation to guarantee that we are not
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;; dividing by 0.
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(define_insn_and_split "<FP16_BINARY_NAME>bf3"
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(define_insn_and_split "<fp16_binary_name>bf3"
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[(set (match_operand:BF 0 "vsx_register_operand" "=wa,wa,wa")
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(FP16_BINARY:BF
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(fp16_binary_op:BF
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(match_operand:BF 1 "vsx_register_operand" "wa,wa,wa")
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(match_operand:BF 2 "fp16_reg_or_constant_operand" "wa,j,eP")))
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(clobber (match_scratch:V4SF 3 "=&wa,&wa,&wa"))
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@ -468,7 +469,7 @@
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emit_insn (gen_xvcvbf16spn_bf (tmp2, tmp2));
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/* Do the operation in V4SFmode. */
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emit_insn (gen_<FP16_BINARY_NAME>v4sf3 (tmp0, tmp1, tmp2));
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emit_insn (gen_<fp16_binary_name>v4sf3 (tmp0, tmp1, tmp2));
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/* Convert V4SF result back to scalar mode. */
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emit_insn (gen_xvcvspbf16_bf (op0, tmp0));
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