mirror of git://gcc.gnu.org/git/gcc.git
[NDS32] Optimize movmem and setmem operations.
gcc/ * config/nds32/nds32-intrinsic.md (unaligned_storedi): Modify patterns implementation. (unaligned_store_dw): Ditto. * config/nds32/nds32-memory-manipulation.c (nds32_expand_movmemsi_loop_known_size): Refactoring implementation. (nds32_gen_dup_4_byte_to_word_value): Rename to ... (nds32_gen_dup_4_byte_to_word_value_aux): ... this. (emit_setmem_word_loop): Rename to ... (emit_setmem_doubleword_loop): ... this. (nds32_gen_dup_4_byte_to_word_value): New function. (nds32_gen_dup_8_byte_to_double_word_value): New function. (nds32_expand_setmem_loop): Refine implementation. (nds32_expand_setmem_loop_v3m): Ditto. * config/nds32/nds32-multiple.md (unaligned_store_update_base_dw): New pattern. Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com> From-SVN: r260805
This commit is contained in:
Monk Chiang
Chung-Ju Wu
parent
0be3bad705
commit
8889fbe542
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@ -1,3 +1,22 @@
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2018-05-27 Monk Chiang <sh.chiang04@gmail.com>
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Chung-Ju Wu <jasonwucj@gmail.com>
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* config/nds32/nds32-intrinsic.md (unaligned_storedi): Modify patterns
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implementation.
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(unaligned_store_dw): Ditto.
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* config/nds32/nds32-memory-manipulation.c
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(nds32_expand_movmemsi_loop_known_size): Refactoring implementation.
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(nds32_gen_dup_4_byte_to_word_value): Rename to ...
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(nds32_gen_dup_4_byte_to_word_value_aux): ... this.
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(emit_setmem_word_loop): Rename to ...
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(emit_setmem_doubleword_loop): ... this.
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(nds32_gen_dup_4_byte_to_word_value): New function.
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(nds32_gen_dup_8_byte_to_double_word_value): New function.
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(nds32_expand_setmem_loop): Refine implementation.
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(nds32_expand_setmem_loop_v3m): Ditto.
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* config/nds32/nds32-multiple.md (unaligned_store_update_base_dw): New
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pattern.
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2018-05-27 Chung-Ju Wu <jasonwucj@gmail.com>
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* config/nds32/nds32.md (bswapsi2, bswaphi2): New patterns.
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@ -1596,22 +1596,17 @@
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if (TARGET_ISA_V3M)
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nds32_expand_unaligned_store (operands, DImode);
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else
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emit_insn (gen_unaligned_store_dw (operands[0], operands[1]));
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emit_insn (gen_unaligned_store_dw (gen_rtx_MEM (DImode, operands[0]),
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operands[1]));
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DONE;
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})
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(define_insn "unaligned_store_dw"
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[(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
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(unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))]
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[(set (match_operand:DI 0 "nds32_lmw_smw_base_operand" "=Umw")
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(unspec:DI [(match_operand:DI 1 "register_operand" " r")] UNSPEC_UASTORE_DW))]
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""
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{
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rtx otherops[3];
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otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1]));
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otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
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otherops[2] = operands[0];
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output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops);
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return "";
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return nds32_output_smw_double_word (operands);
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}
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[(set_attr "type" "store")
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(set_attr "length" "4")]
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@ -257,8 +257,124 @@ static bool
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nds32_expand_movmemsi_loop_known_size (rtx dstmem, rtx srcmem,
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rtx size, rtx alignment)
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{
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return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem,
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size, alignment);
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rtx dst_base_reg, src_base_reg;
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rtx dst_itr, src_itr;
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rtx dstmem_m, srcmem_m, dst_itr_m, src_itr_m;
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rtx dst_end;
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rtx double_word_mode_loop, byte_mode_loop;
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rtx tmp;
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int start_regno;
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bool align_to_4_bytes = (INTVAL (alignment) & 3) == 0;
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unsigned HOST_WIDE_INT total_bytes = UINTVAL (size);
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if (TARGET_ISA_V3M && !align_to_4_bytes)
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return 0;
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if (TARGET_REDUCED_REGS)
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start_regno = 2;
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else
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start_regno = 16;
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dst_itr = gen_reg_rtx (Pmode);
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src_itr = gen_reg_rtx (Pmode);
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dst_end = gen_reg_rtx (Pmode);
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tmp = gen_reg_rtx (QImode);
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double_word_mode_loop = gen_label_rtx ();
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byte_mode_loop = gen_label_rtx ();
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dst_base_reg = copy_to_mode_reg (Pmode, XEXP (dstmem, 0));
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src_base_reg = copy_to_mode_reg (Pmode, XEXP (srcmem, 0));
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if (total_bytes < 8)
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{
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/* Emit total_bytes less than 8 loop version of movmem.
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add $dst_end, $dst, $size
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move $dst_itr, $dst
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.Lbyte_mode_loop:
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lbi.bi $tmp, [$src_itr], #1
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sbi.bi $tmp, [$dst_itr], #1
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! Not readch upper bound. Loop.
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bne $dst_itr, $dst_end, .Lbyte_mode_loop */
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/* add $dst_end, $dst, $size */
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dst_end = expand_binop (Pmode, add_optab, dst_base_reg, size,
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NULL_RTX, 0, OPTAB_WIDEN);
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/* move $dst_itr, $dst
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move $src_itr, $src */
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emit_move_insn (dst_itr, dst_base_reg);
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emit_move_insn (src_itr, src_base_reg);
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/* .Lbyte_mode_loop: */
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emit_label (byte_mode_loop);
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/* lbi.bi $tmp, [$src_itr], #1 */
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nds32_emit_post_inc_load_store (tmp, src_itr, QImode, true);
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/* sbi.bi $tmp, [$dst_itr], #1 */
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nds32_emit_post_inc_load_store (tmp, dst_itr, QImode, false);
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/* ! Not readch upper bound. Loop.
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bne $dst_itr, $dst_end, .Lbyte_mode_loop */
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emit_cmp_and_jump_insns (dst_itr, dst_end, NE, NULL,
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SImode, 1, byte_mode_loop);
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return true;
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}
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else if (total_bytes % 8 == 0)
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{
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/* Emit multiple of 8 loop version of movmem.
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add $dst_end, $dst, $size
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move $dst_itr, $dst
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move $src_itr, $src
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.Ldouble_word_mode_loop:
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lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr
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smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr
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! move will delete after register allocation
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move $src_itr, $src_itr'
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move $dst_itr, $dst_itr'
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! Not readch upper bound. Loop.
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bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop */
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/* add $dst_end, $dst, $size */
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dst_end = expand_binop (Pmode, add_optab, dst_base_reg, size,
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NULL_RTX, 0, OPTAB_WIDEN);
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/* move $dst_itr, $dst
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move $src_itr, $src */
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emit_move_insn (dst_itr, dst_base_reg);
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emit_move_insn (src_itr, src_base_reg);
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/* .Ldouble_word_mode_loop: */
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emit_label (double_word_mode_loop);
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/* lmw.bim $tmp-begin, [$src_itr], $tmp-end, #0 ! $src_itr' = $src_itr
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smw.bim $tmp-begin, [$dst_itr], $tmp-end, #0 ! $dst_itr' = $dst_itr */
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src_itr_m = src_itr;
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dst_itr_m = dst_itr;
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srcmem_m = srcmem;
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dstmem_m = dstmem;
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nds32_emit_mem_move_block (start_regno, 2,
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&dst_itr_m, &dstmem_m,
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&src_itr_m, &srcmem_m,
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true);
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/* move $src_itr, $src_itr'
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move $dst_itr, $dst_itr' */
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emit_move_insn (dst_itr, dst_itr_m);
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emit_move_insn (src_itr, src_itr_m);
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/* ! Not readch upper bound. Loop.
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bne $double_word_end, $dst_itr, .Ldouble_word_mode_loop */
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emit_cmp_and_jump_insns (dst_end, dst_itr, NE, NULL,
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Pmode, 1, double_word_mode_loop);
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}
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else
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{
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/* Handle size greater than 8, and not a multiple of 8. */
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return nds32_expand_movmemsi_loop_unknown_size (dstmem, srcmem,
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size, alignment);
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}
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return true;
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}
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static bool
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@ -433,10 +549,8 @@ nds32_expand_movmemsi (rtx dstmem, rtx srcmem, rtx total_bytes, rtx alignment)
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/* Auxiliary function for expand setmem pattern. */
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static rtx
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nds32_gen_dup_4_byte_to_word_value (rtx value)
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nds32_gen_dup_4_byte_to_word_value_aux (rtx value, rtx value4word)
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{
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rtx value4word = gen_reg_rtx (SImode);
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gcc_assert (GET_MODE (value) == QImode || CONST_INT_P (value));
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if (CONST_INT_P (value))
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@ -493,7 +607,30 @@ nds32_gen_dup_4_byte_to_word_value (rtx value)
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}
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static rtx
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emit_setmem_word_loop (rtx itr, rtx size, rtx value)
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nds32_gen_dup_4_byte_to_word_value (rtx value)
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{
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rtx value4word = gen_reg_rtx (SImode);
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nds32_gen_dup_4_byte_to_word_value_aux (value, value4word);
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return value4word;
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}
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static rtx
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nds32_gen_dup_8_byte_to_double_word_value (rtx value)
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{
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rtx value4doubleword = gen_reg_rtx (DImode);
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nds32_gen_dup_4_byte_to_word_value_aux (
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value, nds32_di_low_part_subreg(value4doubleword));
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emit_move_insn (nds32_di_high_part_subreg(value4doubleword),
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nds32_di_low_part_subreg(value4doubleword));
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return value4doubleword;
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}
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static rtx
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emit_setmem_doubleword_loop (rtx itr, rtx size, rtx value)
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{
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rtx word_mode_label = gen_label_rtx ();
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rtx word_mode_end_label = gen_label_rtx ();
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@ -502,9 +639,9 @@ emit_setmem_word_loop (rtx itr, rtx size, rtx value)
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rtx word_mode_end = gen_reg_rtx (SImode);
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rtx size_for_word = gen_reg_rtx (SImode);
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/* and $size_for_word, $size, #~3 */
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/* and $size_for_word, $size, #~0x7 */
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size_for_word = expand_binop (SImode, and_optab, size,
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gen_int_mode (~3, SImode),
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gen_int_mode (~0x7, SImode),
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NULL_RTX, 0, OPTAB_WIDEN);
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emit_move_insn (byte_mode_size, size);
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@ -516,8 +653,8 @@ emit_setmem_word_loop (rtx itr, rtx size, rtx value)
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word_mode_end = expand_binop (Pmode, add_optab, itr, size_for_word,
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NULL_RTX, 0, OPTAB_WIDEN);
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/* andi $byte_mode_size, $size, 3 */
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byte_mode_size_tmp = expand_binop (SImode, and_optab, size, GEN_INT (3),
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/* andi $byte_mode_size, $size, 0x7 */
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byte_mode_size_tmp = expand_binop (SImode, and_optab, size, GEN_INT (0x7),
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NULL_RTX, 0, OPTAB_WIDEN);
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emit_move_insn (byte_mode_size, byte_mode_size_tmp);
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@ -527,9 +664,9 @@ emit_setmem_word_loop (rtx itr, rtx size, rtx value)
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/* ! word-mode set loop
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smw.bim $value4word, [$dst_itr], $value4word, 0
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bne $word_mode_end, $dst_itr, .Lword_mode */
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emit_insn (gen_unaligned_store_update_base_w (itr,
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itr,
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value));
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emit_insn (gen_unaligned_store_update_base_dw (itr,
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itr,
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value));
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emit_cmp_and_jump_insns (word_mode_end, itr, NE, NULL,
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Pmode, 1, word_mode_label);
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@ -581,7 +718,7 @@ emit_setmem_byte_loop (rtx itr, rtx size, rtx value, bool need_end)
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static bool
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nds32_expand_setmem_loop (rtx dstmem, rtx size, rtx value)
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{
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rtx value4word;
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rtx value4doubleword;
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rtx value4byte;
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rtx dst;
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rtx byte_mode_size;
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@ -624,7 +761,7 @@ nds32_expand_setmem_loop (rtx dstmem, rtx size, rtx value)
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or $tmp3, $tmp1, $tmp2 ! $tmp3 <- 0x0000abab
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slli $tmp4, $tmp3, 16 ! $tmp4 <- 0xabab0000
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or $val4word, $tmp3, $tmp4 ! $value4word <- 0xabababab */
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value4word = nds32_gen_dup_4_byte_to_word_value (value);
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value4doubleword = nds32_gen_dup_8_byte_to_double_word_value (value);
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/* and $size_for_word, $size, #-4
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beqz $size_for_word, .Lword_mode_end
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@ -637,7 +774,7 @@ nds32_expand_setmem_loop (rtx dstmem, rtx size, rtx value)
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smw.bim $value4word, [$dst], $value4word, 0
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bne $word_mode_end, $dst, .Lword_mode
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.Lword_mode_end: */
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byte_mode_size = emit_setmem_word_loop (dst, size, value4word);
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byte_mode_size = emit_setmem_doubleword_loop (dst, size, value4doubleword);
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/* beqz $byte_mode_size, .Lend
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add $byte_mode_end, $dst, $byte_mode_size
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@ -648,8 +785,8 @@ nds32_expand_setmem_loop (rtx dstmem, rtx size, rtx value)
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bne $byte_mode_end, $dst, .Lbyte_mode
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.Lend: */
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value4byte = simplify_gen_subreg (QImode, value4word, SImode,
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subreg_lowpart_offset (QImode, SImode));
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value4byte = simplify_gen_subreg (QImode, value4doubleword, DImode,
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subreg_lowpart_offset (QImode, DImode));
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emit_setmem_byte_loop (dst, byte_mode_size, value4byte, false);
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@ -666,14 +803,15 @@ nds32_expand_setmem_loop_v3m (rtx dstmem, rtx size, rtx value)
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rtx byte_loop_size = gen_reg_rtx (SImode);
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rtx remain_size = gen_reg_rtx (SImode);
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rtx new_base_reg;
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rtx value4byte, value4word;
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rtx value4byte, value4doubleword;
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rtx byte_mode_size;
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rtx last_byte_loop_label = gen_label_rtx ();
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size = force_reg (SImode, size);
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value4word = nds32_gen_dup_4_byte_to_word_value (value);
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value4byte = simplify_gen_subreg (QImode, value4word, SImode, 0);
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value4doubleword = nds32_gen_dup_8_byte_to_double_word_value (value);
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value4byte = simplify_gen_subreg (QImode, value4doubleword, DImode,
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subreg_lowpart_offset (QImode, DImode));
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emit_move_insn (byte_loop_size, size);
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emit_move_insn (byte_loop_base, base_reg);
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@ -701,9 +839,9 @@ nds32_expand_setmem_loop_v3m (rtx dstmem, rtx size, rtx value)
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emit_insn (gen_subsi3 (remain_size, size, need_align_bytes));
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/* Set memory word by word. */
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byte_mode_size = emit_setmem_word_loop (new_base_reg,
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remain_size,
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value4word);
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byte_mode_size = emit_setmem_doubleword_loop (new_base_reg,
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remain_size,
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value4doubleword);
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emit_move_insn (byte_loop_base, new_base_reg);
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emit_move_insn (byte_loop_size, byte_mode_size);
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@ -2854,6 +2854,25 @@
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(set_attr "length" "4")]
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)
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(define_expand "unaligned_store_update_base_dw"
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[(parallel [(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 8)))
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(set (mem:DI (match_dup 1))
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(unspec:DI [(match_operand:DI 2 "register_operand" "r")] UNSPEC_UASTORE_DW))])]
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""
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{
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/* DO NOT emit unaligned_store_w_m immediately since web pass don't
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recognize post_inc, try it again after GCC 5.0.
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REF: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63156 */
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emit_insn (gen_unaligned_store_dw (gen_rtx_MEM (DImode, operands[1]), operands[2]));
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emit_insn (gen_addsi3 (operands[0], operands[1], gen_int_mode (8, Pmode)));
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DONE;
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}
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[(set_attr "type" "store_multiple")
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(set_attr "combo" "2")
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(set_attr "length" "4")]
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)
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(define_insn "*stmsi25"
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[(match_parallel 0 "nds32_store_multiple_operation"
|
||||
[(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
|
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|
|
|
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Loading…
Reference in New Issue