mirror of git://gcc.gnu.org/git/gcc.git
[AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP
* config/aarch64/aarch64.c (aarch64_classify_address): Use DImode when
performing aarch64_offset_7bit_signed_scaled_p check for TImode LDP/STP
addresses.
* gcc.target/aarch64/ldp_stp_unaligned_1.c: New test.
From-SVN: r238938
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2016-08-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64.c (aarch64_classify_address): Use DImode when
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performing aarch64_offset_7bit_signed_scaled_p check for TImode LDP/STP
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addresses.
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2016-08-01 Virendra Pathak <virendra.pathak@broadcom.com>
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* config/aarch64/aarch64.c (vulcan_tunings): Update
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@ -3994,9 +3994,11 @@ aarch64_classify_address (struct aarch64_address_info *info,
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X,X: 7-bit signed scaled offset
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Q: 9-bit signed offset
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We conservatively require an offset representable in either mode.
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*/
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When performing the check for pairs of X registers i.e. LDP/STP
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pass down DImode since that is the natural size of the LDP/STP
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instruction memory accesses. */
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if (mode == TImode || mode == TFmode)
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return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
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return (aarch64_offset_7bit_signed_scaled_p (DImode, offset)
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&& offset_9bit_signed_unscaled_p (mode, offset));
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/* A 7bit offset check because OImode will emit a ldp/stp
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@ -1,3 +1,7 @@
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2016-08-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/aarch64/ldp_stp_unaligned_1.c: New test.
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2016-08-01 Jan Beulich <jbeulich@suse.com>
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* gcc.dg/vshift-6.c, gcc.dg/vshift-7.c: New.
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@ -0,0 +1,20 @@
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/* { dg-options "-O2" } */
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/* Check that we can use a REG + IMM addressing mode when moving an unaligned
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TImode value to and from memory. */
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struct foo
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{
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long long b;
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__int128 a;
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} __attribute__ ((packed));
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void
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bar (struct foo *p, struct foo *q)
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{
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p->a = q->a;
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}
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/* { dg-final { scan-assembler-not "add\tx\[0-9\]+, x\[0-9\]+" } } */
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/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
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/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
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