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vec-all-ne-0.c: New test. 

gcc/testsuite/ChangeLog:

2016-10-18  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* gcc.target/powerpc/vsu/vec-all-ne-0.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-1.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-10.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-11.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-12.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-13.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-14.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-2.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-3.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-4.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-5.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-6.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-7.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-8.c: New test.
	* gcc.target/powerpc/vsu/vec-all-ne-9.c: New test.
	* gcc.target/powerpc/vsu/vec-all-nez-1.c: New test.
	* gcc.target/powerpc/vsu/vec-all-nez-2.c: New test.
	* gcc.target/powerpc/vsu/vec-all-nez-3.c: New test.
	* gcc.target/powerpc/vsu/vec-all-nez-4.c: New test.
	* gcc.target/powerpc/vsu/vec-all-nez-5.c: New test.
	* gcc.target/powerpc/vsu/vec-all-nez-6.c: New test.
	* gcc.target/powerpc/vsu/vec-all-nez-7.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-0.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-1.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-10.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-11.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-12.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-13.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-14.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-2.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-3.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-4.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-5.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-6.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-7.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-8.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eq-9.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eqz-1.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eqz-2.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eqz-3.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eqz-4.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eqz-5.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eqz-6.c: New test.
	* gcc.target/powerpc/vsu/vec-any-eqz-7.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-0.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-1.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-2.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-3.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-4.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-5.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-6.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-8.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpne-9.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpnez-1.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpnez-2.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpnez-3.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpnez-4.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpnez-5.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpnez-6.c: New test.
	* gcc.target/powerpc/vsu/vec-cmpnez-7.c: New test.
	* gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: New test.
	* gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: New test.
	* gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: New test.
	* gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: New test.
	* gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: New test.
	* gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-0.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-1.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-10.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-11.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-12.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-13.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-2.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-3.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-4.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-5.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-6.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-7.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-8.c: New test.
	* gcc.target/powerpc/vsu/vec-xl-len-9.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-0.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-1.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-2.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-3.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-4.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-5.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-6.c: New test.
	* gcc.target/powerpc/vsu/vec-xlx-7.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-0.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-1.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-2.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-3.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-4.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-5.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-6.c: New test.
	* gcc.target/powerpc/vsu/vec-xrx-7.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-0.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-1.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-10.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-11.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-12.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-13.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-2.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-3.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-4.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-5.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-6.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-7.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-8.c: New test.
	* gcc.target/powerpc/vsu/vec-xst-len-9.c: New test.
	* gcc.target/powerpc/vsu/vsu.exp: New file.

gcc/ChangeLog:

2016-10-18  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	* config/rs6000/altivec.h (vec_xl_len): New macro.
	(vec_xst_len): New macro.
	(vec_cmpnez): New macro.
	(vec_cntlz_lsbb): New macro.
	(vec_cnttz_lsbb): New macro.
	(vec_xlx): New macro.
	(vec_xrx): New macro.
	(vec_all_nez): New C++ predicate template.
	(vec_any_eqz): New C++ predicate template.
	(vec_all_ne): Revised C++ predicate template under _ARCH_PWR9
	conditional compilation.
	(vec_any_eq): Revised C++ predicate template under _ARCH_PWR9
	conditional compilation.
	(vec_all_nez): New macro.
	(vec_any_eqz): New macro.
	(vec_all_ne): Revised macro under _ARCH_PWR9 conditional
	compilation.
	(vec_any_eq): Revised macro under _ARCH_PWR9 conditional
	compilation.
	* config/rs6000/vector.md (VI): Moved this mode iterator
	definition from altivec.md to vector.md.
	(UNSPEC_NEZ_P): New value.
	(vector_ne_<mode>_p): New expansion for implementation of
	vec_all_ne and vec_any_eq built-in functions.
	(vector_nez_<mode>_p): New expansion for implementation of
	vec_all_nez and vec_any_eqz built-in functions.
	(vector_ne_v2di_p): New expansion for implementation of vec_all_ne
	and vec_any_eq built-in function.
	(cr6_test_for_zero): New commentary to explain this expansion.
	(cr6_test_for_zero_reverse): New commentary to explain this expansion.
	(cr6_test_for_lt): New commentary to explain this expansion.
	(cr6_test_for_lt_reverse): New commentary to explain this
	expansion.
	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	overloaded function prototypes for vec_all_ne, vec_all_nez,
	vec_any_eq, vec_any_eqz, vec_cmpnez, vec_cntlz_lsbb,
	vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx, and vec_xrx
	built-in functions.
	(altivec_resolve_overloaded_builtin): Modify the handling of
	ALTIVEC_BUILTIN_VEC_CMPNE to use the Power9 instructions when
	the compiler is configured to support TARGET_P9_VECTOR.
	* config/rs6000/rs6000-builtin.def (BU_ALTIVEC_P): Add commentary
	to explain the special processing that is given to predicate
	built-ins introduced using this macro.
	(BU_ALTIVEC_OVERLOAD_P): Add commentary to alert maintainers to
	the special processing given to predicate built-ins introduced
	using this macro.
	(BU_VSX_P): Likewise.
	(BU_P8V_AV_P): Likewise.
	(BU_P9V_AV_P): Likewise.
	(BU_P9V_AV_X): New macro.
	(BU_P9V_64BIT_AV_X): New macro.
	(BU_P9V_VSX_3): New macro.
	(BU_P9V_OVERLOAD_P): New macro.
	(LXVL): New BU_P9V_64BIT_VSX_2.
	(VEXTUBLX): New BU_P9V_AV_2.
	(VEXTUBRX): Likewise.
	(VEXTUHLX): Likewise.
	(VEXTUHRX): Likewise.
	(VEXTUWLX): Likewise.
	(VEXTUWRX): Likewise.
	(STXVL): New BU_P9V_64BIT_AV_X.
	(VCLZLSBB): New BU_P9V_AV_1.
	(VCTZLSBB): Likewise.
	(CMPNEB): New BU_P9V_AV_2.
	(CMPNEH): Likewise.
	(CMPNEW): Likewise.
	(CMPNEF): Likewise.
	(CMPNED): Likewise.
	(VCMPNEB_P): New BU_P9V_AV_P.
	(VCMPNEH_P): Likewise.
	(VCMPNEW_P): Likewise.
	(VCMPNED_P): Likewise.
	(VCMPNEFP_P): Likewise.
	(VCMPNEDP_P): Likewise.
	(CMPNEZB): New BU_P9V_AV_2.
	(CMPNEZH): Likewise.
	(CMPNEZW): Likewise.
	(VCMPNEZB_P): New BU_P9V_AV_P.
	(VCMPNEZH_P): Likewise.
	(VCMPNEZW_P): Likewise.
	(LXVL): New BU_P9V_OVERLOAD_2.
	(STXVL): New BU_P9V_OVERLOAD_3.
	(VEXTULX): New BU_P9V_OVERLOAD_2.
	(VEXTURX): Likewise.
	(CMPNEZ): Likewise.
	(VCMPNEZ_P): New BU_P9V_OVERLOAD_P.
	(VCMPNE_P): Likewise.
	(VCLZLSBB): New BU_P9V_OVERLOAD_1.
	(VCTZLSBB): Likewise.
	* config/rs6000/rs6000.c (altivec_expand_predicate_builtin): Add
	comment to explain mode used for scratch register.
	(altivec_expand_stxvl_builtin): New function.
	(altivec_expand_builtin): Add case for new constant P9V_BUILTIN_STXVL.
	(altivec_init_builtins): Add initialized variable
	void_ftype_v16qi_pvoid_long and use this type to define the
	built-in function __builtin_altivec_stxvl.
	* config/rs6000/vsx.md (UNSPEC_LXVL): New value.
	(UNSPEC_STXVL): New value.
	(UNSPEC_VCLZLSBB): New value.
	(UNSPEC_VCTZLSBB): New value.
	(UNSPEC_VEXTUBLX): New value.
	(UNSPEC_VEXTUHLX): New value.
	(UNSPEC_VEXTUWLX): New value.
	(UNSPEC_VEXTUBRX): New value.
	(UNSPEC_VEXTUHRX): New value.
	(UNSPEC_VEXTUWRX): New value.
	(UNSPEC_VCMPNEB): New value.
	(UNSPEC_VCMPNEZB): New value.
	(UNSPEC_VCMPNEH): New value.
	(UNSPEC_VCMPNEZH): New value.
	(UNSPEC_VCMPNEW): New value.
	(UNSPEC_VCMPNEZW): New value.
	(*vsx_ne_<mode>_p): New insn for vector test all not equal with
	vector of integer modes.
	(*vsx_ne_<mode>_p): New insn for vector test all not equal with
	vector of float or double modes.
	(*vector_nez_<mode>_p): New insn for vector test all not equal or
	zero.
	(lxvl): New expand for load VSX vector with length.
	(*lxvl): New insn for load VSX vector with length.
	(stxvl): New expand for store VSX vector with length.
	(*stxvl): New insn for store VSX vector with length.
	(vcmpneb): New insn for vector of byte compare not equal.
	(vcmpnezb): New insn for vector of byte compare not equal or zero.
	(vcmpneh): New insn for vector of half word compare not equal.
	(vcmpnezh): New insn for vector of half word compare not equal or
	zero.
	(vcmpnew): New insn for vector of word compare not equal.
	(vcmpne<VSs>): New insn for vector of float or double compare not
	equal.
	(vcmpnezw): New insn for vector of word compare not equal or zero.
	(vclzlsbb): New insn for vector count leading zero
	least-significant bits byte.
	(vctzlsbb): New insn for vector count trailing zero least
	signficant bits byte.
	(vextublx): New insn for vector extract unsigned byte left
	indexed.
	(vextubrx): New insn for vector extract unsigned byte right
	indexed.
	(vextuhlx): New insn for vector extract unsigned half word left
	indexed.
	(vextuhrx): New insn for vector extract unsigned half word right
	indexed.
	(vextuwlx): New insn for vector extract unsigned word left
	indexed.
	(vextuwrx): New insn for vector extract unsigned word right
	indexed.
	* config/rs6000/rs6000.h (RS6000_BTC_CONST): Enhance comment to
	clarify intent of this constant.
	* config/rs6000/altivec.md (VI): Move this mode iterator to vsx.md.
	* doc/extend.texi (PowerPC Altivec Built-in Functions): Add
	documentation for vec_all_nez, vec_any_eqz, vec_cmpnez,
	vec_cntlz_lsbb, vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx,
	and vec_xrx functions.

From-SVN: r241314
This commit is contained in:
Kelvin Nilsen 2016-10-18 19:31:38 +00:00
parent 2a26adf1d8
commit 902cb7b191
122 changed files with 3307 additions and 43 deletions
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158
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@ -1,3 +1,161 @@
2016-10-18 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/altivec.h (vec_xl_len): New macro.
(vec_xst_len): New macro.
(vec_cmpnez): New macro.
(vec_cntlz_lsbb): New macro.
(vec_cnttz_lsbb): New macro.
(vec_xlx): New macro.
(vec_xrx): New macro.
(vec_all_nez): New C++ predicate template.
(vec_any_eqz): New C++ predicate template.
(vec_all_ne): Revised C++ predicate template under _ARCH_PWR9
conditional compilation.
(vec_any_eq): Revised C++ predicate template under _ARCH_PWR9
conditional compilation.
(vec_all_nez): New macro.
(vec_any_eqz): New macro.
(vec_all_ne): Revised macro under _ARCH_PWR9 conditional
compilation.
(vec_any_eq): Revised macro under _ARCH_PWR9 conditional
compilation.
* config/rs6000/vector.md (VI): Moved this mode iterator
definition from altivec.md to vector.md.
(UNSPEC_NEZ_P): New value.
(vector_ne_<mode>_p): New expansion for implementation of
vec_all_ne and vec_any_eq built-in functions.
(vector_nez_<mode>_p): New expansion for implementation of
vec_all_nez and vec_any_eqz built-in functions.
(vector_ne_v2di_p): New expansion for implementation of vec_all_ne
and vec_any_eq built-in function.
(cr6_test_for_zero): New commentary to explain this expansion.
(cr6_test_for_zero_reverse): New commentary to explain this expansion.
(cr6_test_for_lt): New commentary to explain this expansion.
(cr6_test_for_lt_reverse): New commentary to explain this
expansion.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
overloaded function prototypes for vec_all_ne, vec_all_nez,
vec_any_eq, vec_any_eqz, vec_cmpnez, vec_cntlz_lsbb,
vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx, and vec_xrx
built-in functions.
(altivec_resolve_overloaded_builtin): Modify the handling of
ALTIVEC_BUILTIN_VEC_CMPNE to use the Power9 instructions when
the compiler is configured to support TARGET_P9_VECTOR.
* config/rs6000/rs6000-builtin.def (BU_ALTIVEC_P): Add commentary
to explain the special processing that is given to predicate
built-ins introduced using this macro.
(BU_ALTIVEC_OVERLOAD_P): Add commentary to alert maintainers to
the special processing given to predicate built-ins introduced
using this macro.
(BU_VSX_P): Likewise.
(BU_P8V_AV_P): Likewise.
(BU_P9V_AV_P): Likewise.
(BU_P9V_AV_X): New macro.
(BU_P9V_64BIT_AV_X): New macro.
(BU_P9V_VSX_3): New macro.
(BU_P9V_OVERLOAD_P): New macro.
(LXVL): New BU_P9V_64BIT_VSX_2.
(VEXTUBLX): New BU_P9V_AV_2.
(VEXTUBRX): Likewise.
(VEXTUHLX): Likewise.
(VEXTUHRX): Likewise.
(VEXTUWLX): Likewise.
(VEXTUWRX): Likewise.
(STXVL): New BU_P9V_64BIT_AV_X.
(VCLZLSBB): New BU_P9V_AV_1.
(VCTZLSBB): Likewise.
(CMPNEB): New BU_P9V_AV_2.
(CMPNEH): Likewise.
(CMPNEW): Likewise.
(CMPNEF): Likewise.
(CMPNED): Likewise.
(VCMPNEB_P): New BU_P9V_AV_P.
(VCMPNEH_P): Likewise.
(VCMPNEW_P): Likewise.
(VCMPNED_P): Likewise.
(VCMPNEFP_P): Likewise.
(VCMPNEDP_P): Likewise.
(CMPNEZB): New BU_P9V_AV_2.
(CMPNEZH): Likewise.
(CMPNEZW): Likewise.
(VCMPNEZB_P): New BU_P9V_AV_P.
(VCMPNEZH_P): Likewise.
(VCMPNEZW_P): Likewise.
(LXVL): New BU_P9V_OVERLOAD_2.
(STXVL): New BU_P9V_OVERLOAD_3.
(VEXTULX): New BU_P9V_OVERLOAD_2.
(VEXTURX): Likewise.
(CMPNEZ): Likewise.
(VCMPNEZ_P): New BU_P9V_OVERLOAD_P.
(VCMPNE_P): Likewise.
(VCLZLSBB): New BU_P9V_OVERLOAD_1.
(VCTZLSBB): Likewise.
* config/rs6000/rs6000.c (altivec_expand_predicate_builtin): Add
comment to explain mode used for scratch register.
(altivec_expand_stxvl_builtin): New function.
(altivec_expand_builtin): Add case for new constant P9V_BUILTIN_STXVL.
(altivec_init_builtins): Add initialized variable
void_ftype_v16qi_pvoid_long and use this type to define the
built-in function __builtin_altivec_stxvl.
* config/rs6000/vsx.md (UNSPEC_LXVL): New value.
(UNSPEC_STXVL): New value.
(UNSPEC_VCLZLSBB): New value.
(UNSPEC_VCTZLSBB): New value.
(UNSPEC_VEXTUBLX): New value.
(UNSPEC_VEXTUHLX): New value.
(UNSPEC_VEXTUWLX): New value.
(UNSPEC_VEXTUBRX): New value.
(UNSPEC_VEXTUHRX): New value.
(UNSPEC_VEXTUWRX): New value.
(UNSPEC_VCMPNEB): New value.
(UNSPEC_VCMPNEZB): New value.
(UNSPEC_VCMPNEH): New value.
(UNSPEC_VCMPNEZH): New value.
(UNSPEC_VCMPNEW): New value.
(UNSPEC_VCMPNEZW): New value.
(*vsx_ne_<mode>_p): New insn for vector test all not equal with
vector of integer modes.
(*vsx_ne_<mode>_p): New insn for vector test all not equal with
vector of float or double modes.
(*vector_nez_<mode>_p): New insn for vector test all not equal or
zero.
(lxvl): New expand for load VSX vector with length.
(*lxvl): New insn for load VSX vector with length.
(stxvl): New expand for store VSX vector with length.
(*stxvl): New insn for store VSX vector with length.
(vcmpneb): New insn for vector of byte compare not equal.
(vcmpnezb): New insn for vector of byte compare not equal or zero.
(vcmpneh): New insn for vector of half word compare not equal.
(vcmpnezh): New insn for vector of half word compare not equal or
zero.
(vcmpnew): New insn for vector of word compare not equal.
(vcmpne<VSs>): New insn for vector of float or double compare not
equal.
(vcmpnezw): New insn for vector of word compare not equal or zero.
(vclzlsbb): New insn for vector count leading zero
least-significant bits byte.
(vctzlsbb): New insn for vector count trailing zero least
signficant bits byte.
(vextublx): New insn for vector extract unsigned byte left
indexed.
(vextubrx): New insn for vector extract unsigned byte right
indexed.
(vextuhlx): New insn for vector extract unsigned half word left
indexed.
(vextuhrx): New insn for vector extract unsigned half word right
indexed.
(vextuwlx): New insn for vector extract unsigned word left
indexed.
(vextuwrx): New insn for vector extract unsigned word right
indexed.
* config/rs6000/rs6000.h (RS6000_BTC_CONST): Enhance comment to
clarify intent of this constant.
* config/rs6000/altivec.md (VI): Move this mode iterator to vsx.md.
* doc/extend.texi (PowerPC Altivec Built-in Functions): Add
documentation for vec_all_nez, vec_any_eqz, vec_cmpnez,
vec_cntlz_lsbb, vec_cnttz_lsbb, vec_xl_len, vec_xst_len, vec_xlx,
and vec_xrx functions.
2016-10-18 Andrew Pinski <apinski@cavium.com>
PR tree-opt/65950

34
gcc/config/rs6000/altivec.h
View File

@ -426,6 +426,18 @@
#define scalar_cmp_exp_eq __builtin_vec_scalar_cmp_exp_eq
#define scalar_cmp_exp_unordered __builtin_vec_scalar_cmp_exp_unordered
#ifdef _ARCH_PPC64
#define vec_xl_len __builtin_vec_lxvl
#define vec_xst_len __builtin_vec_stxvl
#endif
#define vec_cmpnez __builtin_vec_vcmpnez
#define vec_cntlz_lsbb __builtin_vec_vclzlsbb
#define vec_cnttz_lsbb __builtin_vec_vctzlsbb
#define vec_xlx __builtin_vec_vextulx
#define vec_xrx __builtin_vec_vexturx
#endif
/* Predicates.
@ -489,10 +501,23 @@ __altivec_unary_pred(vec_any_numeric,
__altivec_scalar_pred(vec_all_eq,
__builtin_vec_vcmpeq_p (__CR6_LT, a1, a2))
#ifndef _ARCH_PWR9
__altivec_scalar_pred(vec_all_ne,
__builtin_vec_vcmpeq_p (__CR6_EQ, a1, a2))
__altivec_scalar_pred(vec_any_eq,
__builtin_vec_vcmpeq_p (__CR6_EQ_REV, a1, a2))
#else
__altivec_scalar_pred(vec_all_nez,
__builtin_vec_vcmpnez_p (__CR6_LT, a1, a2))
__altivec_scalar_pred(vec_any_eqz,
__builtin_vec_vcmpnez_p (__CR6_LT_REV, a1, a2))
__altivec_scalar_pred(vec_all_ne,
__builtin_vec_vcmpne_p (__CR6_LT, a1, a2))
__altivec_scalar_pred(vec_any_eq,
__builtin_vec_vcmpne_p (__CR6_LT_REV, a1, a2))
#endif
__altivec_scalar_pred(vec_any_ne,
__builtin_vec_vcmpeq_p (__CR6_LT_REV, a1, a2))
@ -552,8 +577,17 @@ __altivec_scalar_pred(vec_any_nle,
#define vec_any_numeric(a1) __builtin_vec_vcmpeq_p (__CR6_EQ_REV, (a1), (a1))
#define vec_all_eq(a1, a2) __builtin_vec_vcmpeq_p (__CR6_LT, (a1), (a2))
#ifdef _ARCH_PWR9
#define vec_all_nez(a1, a2) __builtin_vec_vcmpnez_p (__CR6_LT, (a1), (a2))
#define vec_any_eqz(a1, a2) __builtin_vec_vcmpnez_p (__CR6_LT_REV, (a1), (a2))
#define vec_all_ne(a1, a2) __builtin_vec_vcmpne_p (__CR6_LT, (a1), (a2))
#define vec_any_eq(a1, a2) __builtin_vec_vcmpne_p (__CR6_LT_REV, (a1), (a2))
#else
#define vec_all_ne(a1, a2) __builtin_vec_vcmpeq_p (__CR6_EQ, (a1), (a2))
#define vec_any_eq(a1, a2) __builtin_vec_vcmpeq_p (__CR6_EQ_REV, (a1), (a2))
#endif
#define vec_any_ne(a1, a2) __builtin_vec_vcmpeq_p (__CR6_LT_REV, (a1), (a2))
#define vec_all_gt(a1, a2) __builtin_vec_vcmpgt_p (__CR6_LT, (a1), (a2))

4
gcc/config/rs6000/altivec.md
View File

@ -163,9 +163,7 @@
UNSPECV_DSS
])
;; Vec int modes
(define_mode_iterator VI [V4SI V8HI V16QI])
;; Like VI, but add ISA 2.07 integer vector ops
;; Like VI, defined in vector.md, but add ISA 2.07 integer vector ops
(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])
;; Short vec in modes
(define_mode_iterator VIshort [V8HI V16QI])

132
gcc/config/rs6000/rs6000-builtin.def
View File

@ -137,6 +137,32 @@
| RS6000_BTC_DST), \
CODE_FOR_ ## ICODE) /* ICODE */
/* All builtins defined with the RS6000_BUILTIN_P macro expect three
arguments, the first of which is an integer constant that clarifies
the implementation's use of CR6 flags. The integer constant
argument may have four values: __CR6_EQ (0) means the predicate is
considered true if the equality-test flag of the CR6 condition
register is true following execution of the code identified by the
ICODE pattern, __CR_EQ_REV (1) means the predicate is considered
true if the equality-test flag is false, __CR6_LT (2) means the
predicate is considered true if the less-than-test flag is true, and
__CR6_LT_REV (3) means the predicate is considered true if the
less-than-test flag is false. For all builtins defined by this
macro, the pattern selected by ICODE expects three operands, a
target and two inputs and is presumed to overwrite the flags of
condition register CR6 as a side effect of computing a result into
the target register. However, the built-in invocation provides
four operands, a target, an integer constant mode, and two inputs.
The second and third operands of the built-in function's invocation
are automatically mapped into operands 1 and 2 of the pattern
identifed by the ICODE argument and additional code is emitted,
depending on the value of the constant integer first argument.
This special processing happens within the implementation of
altivec_expand_predicate_builtin(), which is defined within
rs6000.c. The implementation of altivec_expand_predicate_builtin()
allocates a scratch register having the same mode as operand 0 to hold
the result produced by evaluating ICODE. */
#define BU_ALTIVEC_P(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_P (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
@ -203,6 +229,7 @@
| RS6000_BTC_DST), \
CODE_FOR_nothing) /* ICODE */
/* See the comment on BU_ALTIVEC_P. */
#define BU_ALTIVEC_OVERLOAD_P(ENUM, NAME) \
RS6000_BUILTIN_P (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \
"__builtin_vec_" NAME, /* NAME */ \
@ -252,6 +279,7 @@
| RS6000_BTC_ABS), \
CODE_FOR_ ## ICODE) /* ICODE */
/* See the comment on BU_ALTIVEC_P. */
#define BU_VSX_P(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_P (VSX_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_vsx_" NAME, /* NAME */ \
@ -338,6 +366,7 @@
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
/* See the comment on BU_ALTIVEC_P. */
#define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
@ -781,6 +810,7 @@
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
/* See the comment on BU_ALTIVEC_P. */
#define BU_P9V_AV_P(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_P (P9V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
@ -789,6 +819,23 @@
| RS6000_BTC_PREDICATE), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P9V_AV_X(ENUM, NAME, ATTR) \
RS6000_BUILTIN_X (P9V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
RS6000_BTM_P9_VECTOR, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_nothing) /* ICODE */
#define BU_P9V_64BIT_AV_X(ENUM, NAME, ATTR) \
RS6000_BUILTIN_X (P9V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_altivec_" NAME, /* NAME */ \
(RS6000_BTM_P9_VECTOR \
| RS6000_BTM_64BIT), /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_nothing) /* ICODE */
/* For the instructions encoded as VSX instructions use __builtin_vsx as the
builtin name. */
#define BU_P9V_VSX_1(ENUM, NAME, ATTR, ICODE) \
@ -825,6 +872,23 @@
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P9V_VSX_3(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_3 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P9_VECTOR, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
/* See the comment on BU_ALTIVEC_P. */
#define BU_P9V_OVERLOAD_P(ENUM, NAME) \
RS6000_BUILTIN_P (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \
"__builtin_vec_" NAME, /* NAME */ \
RS6000_BTM_ALTIVEC, /* MASK */ \
(RS6000_BTC_OVERLOADED /* ATTR */ \
| RS6000_BTC_PREDICATE), \
CODE_FOR_nothing) /* ICODE */
#define BU_P9V_OVERLOAD_1(ENUM, NAME) \
RS6000_BUILTIN_1 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \
"__builtin_vec_" NAME, /* NAME */ \
@ -1893,6 +1957,74 @@ BU_P9V_OVERLOAD_2 (VIE, "insert_exp")
BU_P9V_OVERLOAD_2 (VIEDP, "insert_exp_dp")
BU_P9V_OVERLOAD_2 (VIESP, "insert_exp_sp")
/* 2 argument vector functions added in ISA 3.0 (power9). */
BU_P9V_64BIT_VSX_2 (LXVL, "lxvl", CONST, lxvl)
BU_P9V_AV_2 (VEXTUBLX, "vextublx", CONST, vextublx)
BU_P9V_AV_2 (VEXTUBRX, "vextubrx", CONST, vextubrx)
BU_P9V_AV_2 (VEXTUHLX, "vextuhlx", CONST, vextuhlx)
BU_P9V_AV_2 (VEXTUHRX, "vextuhrx", CONST, vextuhrx)
BU_P9V_AV_2 (VEXTUWLX, "vextuwlx", CONST, vextuwlx)
BU_P9V_AV_2 (VEXTUWRX, "vextuwrx", CONST, vextuwrx)
/* 3 argument vector functions returning void, treated as SPECIAL,
added in ISA 3.0 (power9). */
BU_P9V_64BIT_AV_X (STXVL, "stxvl", MISC)
/* 1 argument vector functions added in ISA 3.0 (power9). */
BU_P9V_AV_1 (VCLZLSBB, "vclzlsbb", CONST, vclzlsbb)
BU_P9V_AV_1 (VCTZLSBB, "vctzlsbb", CONST, vctzlsbb)
/* Built-in support for Power9 "VSU option" string operations includes
new awareness of the "vector compare not equal" (vcmpneb, vcmpneb.,
vcmpneh, vcmpneh., vcmpnew, vcmpnew.) and "vector compare
not equal or zero" (vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
vcmpnezw, vcmpnezw.) instructions. For consistency with existing
infrastructure, this new awareness is integrated in the style of
earlier implementations of the __builtin_vec_cmpne and
__builtin_vec_cmpeq_p functions. */
BU_P9V_AV_2 (CMPNEB, "vcmpneb", CONST, vcmpneb)
BU_P9V_AV_2 (CMPNEH, "vcmpneh", CONST, vcmpneh)
BU_P9V_AV_2 (CMPNEW, "vcmpnew", CONST, vcmpnew)
BU_P9V_AV_2 (CMPNEF, "vcmpnef", CONST, vcmpnesp)
BU_P9V_AV_2 (CMPNED, "vcmpned", CONST, vcmpnedp)
BU_P9V_AV_P (VCMPNEB_P, "vcmpneb_p", CONST, vector_ne_v16qi_p)
BU_P9V_AV_P (VCMPNEH_P, "vcmpneh_p", CONST, vector_ne_v8hi_p)
BU_P9V_AV_P (VCMPNEW_P, "vcmpnew_p", CONST, vector_ne_v4si_p)
BU_P9V_AV_P (VCMPNED_P, "vcmpned_p", CONST, vector_ne_v2di_p)
BU_P9V_AV_P (VCMPNEFP_P, "vcmpnefp_p", CONST, vector_ne_v4sf_p)
BU_P9V_AV_P (VCMPNEDP_P, "vcmpnedp_p", CONST, vector_ne_v2df_p)
BU_P9V_AV_2 (CMPNEZB, "vcmpnezb", CONST, vcmpnezb)
BU_P9V_AV_2 (CMPNEZH, "vcmpnezh", CONST, vcmpnezh)
BU_P9V_AV_2 (CMPNEZW, "vcmpnezw", CONST, vcmpnezw)
BU_P9V_AV_P (VCMPNEZB_P, "vcmpnezb_p", CONST, vector_nez_v16qi_p)
BU_P9V_AV_P (VCMPNEZH_P, "vcmpnezh_p", CONST, vector_nez_v8hi_p)
BU_P9V_AV_P (VCMPNEZW_P, "vcmpnezw_p", CONST, vector_nez_v4si_p)
/* ISA 3.0 Vector scalar overloaded 2 argument functions */
BU_P9V_OVERLOAD_2 (LXVL, "lxvl")
/* ISA 3.0 Vector scalar overloaded 3 argument functions */
BU_P9V_OVERLOAD_3 (STXVL, "stxvl")
BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx")
BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx")
/* Overloaded CMPNE support was implemented prior to Power 9,
so is not mentioned here. */
BU_P9V_OVERLOAD_2 (CMPNEZ, "vcmpnez")
BU_P9V_OVERLOAD_P (VCMPNEZ_P, "vcmpnez_p")
BU_P9V_OVERLOAD_P (VCMPNE_P, "vcmpne_p")
/* ISA 3.0 Vector scalar overloaded 1 argument functions */
BU_P9V_OVERLOAD_1 (VCLZLSBB, "vclzlsbb")
BU_P9V_OVERLOAD_1 (VCTZLSBB, "vctzlsbb")
/* 2 argument extended divide functions added in ISA 2.06. */
BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si)

410
gcc/config/rs6000/rs6000-c.c
View File

@ -4391,6 +4391,330 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
{ P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V2DF, ~RS6000_BTI_double,
RS6000_BTI_unsigned_long_long, 0 },
{ P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
RS6000_BTI_V4SF, ~RS6000_BTI_float,
RS6000_BTI_unsigned_long_long, 0 },
/* At an appropriate future time, add support for the
RS6000_BTI_Float16 (exact name to be determined) type here. */
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
RS6000_BTI_unsigned_long_long },
{ P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
RS6000_BTI_unsigned_long_long },
/* At an appropriate future time, add support for the
RS6000_BTI_Float16 (exact name to be determined) type here. */
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
RS6000_BTI_bool_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
RS6000_BTI_bool_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
RS6000_BTI_bool_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEF,
RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
{ ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNED,
RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
RS6000_BTI_unsigned_V16QI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_bool_V16QI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
RS6000_BTI_V16QI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI,
RS6000_BTI_bool_V16QI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
RS6000_BTI_bool_V16QI },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
RS6000_BTI_unsigned_V8HI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_bool_V8HI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
RS6000_BTI_V8HI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI,
RS6000_BTI_bool_V8HI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
RS6000_BTI_bool_V8HI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
RS6000_BTI_pixel_V8HI },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
RS6000_BTI_unsigned_V4SI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_bool_V4SI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
RS6000_BTI_V4SI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI,
RS6000_BTI_bool_V4SI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
RS6000_BTI_bool_V4SI },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
RS6000_BTI_unsigned_V2DI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_bool_V2DI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI },
/* The following 2 entries have been deprecated. */
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
RS6000_BTI_V2DI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI,
RS6000_BTI_bool_V2DI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
RS6000_BTI_bool_V2DI },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
{ P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
{ P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI },
{ P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
{ P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI },
{ P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
{ P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI },
{ P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
{ P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_V16QI, 0 },
{ P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, 0 },
{ P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_V8HI, 0 },
{ P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, 0 },
{ P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_V4SI, 0 },
{ P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, 0 },
{ P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
RS6000_BTI_V16QI, 0 },
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V16QI, 0 },
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
RS6000_BTI_V8HI, 0 },
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V8HI, 0 },
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
RS6000_BTI_V4SI, 0 },
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V4SI, 0 },
{ P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
RS6000_BTI_float, RS6000_BTI_UINTSI,
RS6000_BTI_V4SF, 0 },
{ P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
RS6000_BTI_V16QI, 0 },
{ P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V16QI, 0 },
{ P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
RS6000_BTI_V8HI, 0 },
{ P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V8HI, 0 },
{ P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
RS6000_BTI_V4SI, 0 },
{ P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V4SI, 0 },
{ P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
RS6000_BTI_float, RS6000_BTI_UINTSI,
RS6000_BTI_V4SF, 0 },
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
@ -4895,47 +5219,57 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
tree arg1 = (*arglist)[1];
tree arg1_type = TREE_TYPE (arg1);
/* Both arguments must be vectors and the types must match. */
if (arg0_type != arg1_type)
goto bad;
if (TREE_CODE (arg0_type) != VECTOR_TYPE)
goto bad;
switch (TYPE_MODE (TREE_TYPE (arg0_type)))
/* Power9 instructions provide the most efficient implementation of
ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode. */
if (!TARGET_P9_VECTOR
|| (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
|| (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode))
{
/* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
vec_cmpeq (va, vb)). */
/* Note: vec_nand also works but opt changes vec_nand's to vec_nor's
anyway. */
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case SFmode:
case DFmode:
{
/* call = vec_cmpeq (va, vb)
result = vec_nor (call, call). */
vec<tree, va_gc> *params = make_tree_vector ();
vec_safe_push (params, arg0);
vec_safe_push (params, arg1);
tree call = altivec_resolve_overloaded_builtin
(loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ], params);
/* Use save_expr to ensure that operands used more than once
that may have side effects (like calls) are only evaluated
once. */
call = save_expr (call);
params = make_tree_vector ();
vec_safe_push (params, call);
vec_safe_push (params, call);
return altivec_resolve_overloaded_builtin
(loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
}
/* Other types are errors. */
default:
/* Both arguments must be vectors and the types must match. */
if (arg0_type != arg1_type)
goto bad;
if (TREE_CODE (arg0_type) != VECTOR_TYPE)
goto bad;
switch (TYPE_MODE (TREE_TYPE (arg0_type)))
{
/* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
vec_cmpeq (va, vb)). */
/* Note: vec_nand also works but opt changes vec_nand's
to vec_nor's anyway. */
case QImode:
case HImode:
case SImode:
case DImode:
case TImode:
case SFmode:
case DFmode:
{
/* call = vec_cmpeq (va, vb)
result = vec_nor (call, call). */
vec<tree, va_gc> *params = make_tree_vector ();
vec_safe_push (params, arg0);
vec_safe_push (params, arg1);
tree call = altivec_resolve_overloaded_builtin
(loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
params);
/* Use save_expr to ensure that operands used more than once
that may have side effects (like calls) are only evaluated
once. */
call = save_expr (call);
params = make_tree_vector ();
vec_safe_push (params, call);
vec_safe_push (params, call);
return altivec_resolve_overloaded_builtin
(loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
}
/* Other types are errors. */
default:
goto bad;
}
}
/* else, fall through and process the Power9 alternative below */
}
if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)

55
gcc/config/rs6000/rs6000.c
View File

@ -14169,6 +14169,11 @@ altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
op1 = copy_to_mode_reg (mode1, op1);
/* Note that for many of the relevant operations (e.g. cmpne or
cmpeq) with float or double operands, it makes more sense for the
mode of the allocated scratch register to select a vector of
integer. But the choice to copy the mode of operand 0 was made
long ago and there are no plans to change it. */
scratch = gen_reg_rtx (mode0);
pat = GEN_FCN (icode) (scratch, op0, op1);
@ -14503,6 +14508,44 @@ paired_expand_stv_builtin (enum insn_code icode, tree exp)
return NULL_RTX;
}
static rtx
altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
{
rtx pat;
tree arg0 = CALL_EXPR_ARG (exp, 0);
tree arg1 = CALL_EXPR_ARG (exp, 1);
tree arg2 = CALL_EXPR_ARG (exp, 2);
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
rtx op2 = expand_normal (arg2);
machine_mode mode0 = insn_data[icode].operand[0].mode;
machine_mode mode1 = insn_data[icode].operand[1].mode;
machine_mode mode2 = insn_data[icode].operand[2].mode;
if (icode == CODE_FOR_nothing)
/* Builtin not supported on this processor. */
return NULL_RTX;
/* If we got invalid arguments bail out before generating bad rtl. */
if (arg0 == error_mark_node
|| arg1 == error_mark_node
|| arg2 == error_mark_node)
return NULL_RTX;
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
op1 = copy_to_mode_reg (mode1, op1);
if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
op2 = copy_to_mode_reg (mode2, op2);
pat = GEN_FCN (icode) (op0, op1, op2);
if (pat)
emit_insn (pat);
return NULL_RTX;
}
static rtx
altivec_expand_stv_builtin (enum insn_code icode, tree exp)
{
@ -15463,6 +15506,9 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
case ALTIVEC_BUILTIN_STVRXL:
return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
case P9V_BUILTIN_STXVL:
return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
case VSX_BUILTIN_STXVD2X_V1TI:
return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
case VSX_BUILTIN_STXVD2X_V2DF:
@ -17210,6 +17256,12 @@ altivec_init_builtins (void)
= build_function_type_list (void_type_node,
V16QI_type_node, long_integer_type_node,
pvoid_type_node, NULL_TREE);
tree void_ftype_v16qi_pvoid_long
= build_function_type_list (void_type_node,
V16QI_type_node, pvoid_type_node,
long_integer_type_node, NULL_TREE);
tree void_ftype_v8hi_long_pvoid
= build_function_type_list (void_type_node,
V8HI_type_node, long_integer_type_node,
@ -17448,6 +17500,9 @@ altivec_init_builtins (void)
def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
P9V_BUILTIN_STXVL);
/* Add the DST variants. */
d = bdesc_dst;
for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)

3
gcc/config/rs6000/rs6000.h
View File

@ -2694,7 +2694,8 @@ extern int frame_pointer_needed;
#define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
#define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
#define RS6000_BTC_CONST 0x00000100 /* uses no global state. */
#define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
modifies global state. */
#define RS6000_BTC_PURE 0x00000200 /* reads global
state/mem and does
not modify global state. */

92
gcc/config/rs6000/vector.md
View File

@ -61,6 +61,9 @@
;; Vector modes for 64-bit base types
(define_mode_iterator VEC_64 [V2DI V2DF])
;; Vector integer modes
(define_mode_iterator VI [V4SI V8HI V16QI])
;; Base type from vector mode
(define_mode_attr VEC_base [(V16QI "QI")
(V8HI "HI")
@ -80,7 +83,8 @@
;; constants for unspec
(define_c_enum "unspec" [UNSPEC_PREDICATE
UNSPEC_REDUC])
UNSPEC_REDUC
UNSPEC_NEZ_P])
;; Vector reduction code iterators
(define_code_iterator VEC_reduc [plus smin smax])
@ -680,6 +684,75 @@
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; This expansion handles the V16QI, V8HI, and V4SI modes in the
;; implementation of the vec_all_ne and vec_any_eq built-in functions
;; on Power9.
(define_expand "vector_ne_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
(match_operand:VI 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
(set (match_operand:VI 0 "vlogical_operand")
(ne:VI (match_dup 1)
(match_dup 2)))])]
"TARGET_P9_VECTOR"
"")
;; This expansion handles the V16QI, V8HI, and V4SI modes in the
;; implementation of the vec_all_nez and vec_any_eqz built-in
;; functions on Power9.
(define_expand "vector_nez_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(unspec:VI
[(match_operand:VI 1 "vlogical_operand")
(match_operand:VI 2 "vlogical_operand")]
UNSPEC_NEZ_P)]
UNSPEC_PREDICATE))
(set (match_operand:VI 0 "vlogical_operand")
(unspec:VI [(match_dup 1)
(match_dup 2)]
UNSPEC_NEZ_P))])]
"TARGET_P9_VECTOR"
"")
;; This expansion handles the V4DI mode in the implementation of the
;; vec_all_ne and vec_any_eq built-in function on Power9.
;;
;; Since the "xvcmpne<mode>." instruction does not support DImode,
;; we'll use a V4SI comparison, which will set the values of the CR6
;; flags to be the same as if we had performed a DImode comparison.
;; (All of the entries in a V2DI vector are not equal iff all of the
;; entries in the same vector, interpeted as V4SI are not equal, and
;; likewise in the test for "any equal".)
(define_expand "vector_ne_v2di_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(ne:CC (match_operand:V4SI 1 "vlogical_operand")
(match_operand:V4SI 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
(set (match_operand:V4SI 0 "vlogical_operand")
(ne:V4SI (match_dup 1)
(match_dup 2)))])]
"TARGET_P9_VECTOR"
"")
;; This expansion handles the V4SF and V2DF modes in the Power9
;; implementation of the vec_all_ne and vec_any_eq built-in
;; functions.
(define_expand "vector_ne_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(ne:CC (match_operand:VEC_F 1 "vlogical_operand")
(match_operand:VEC_F 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
(set (match_operand:VEC_F 0 "vlogical_operand")
(ne:VEC_F (match_dup 1)
(match_dup 2)))])]
"TARGET_P9_VECTOR"
"")
(define_expand "vector_gt_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
@ -718,6 +791,10 @@
;; AltiVec/VSX predicates.
;; This expansion is triggered during expansion of predicate built-in
;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
;; altivec_expand_predicate_builtin() function when the value of the
;; integer constant first argument equals zero (aka __CR6_EQ in altivec.h).
(define_expand "cr6_test_for_zero"
[(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (reg:CC CR6_REGNO)
@ -725,6 +802,10 @@
"TARGET_ALTIVEC || TARGET_VSX"
"")
;; This expansion is triggered during expansion of predicate built-in
;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
;; altivec_expand_predicate_builtin() function when the value of the
;; integer constant first argument equals one (aka __CR6_EQ_REV in altivec.h).
(define_expand "cr6_test_for_zero_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
(eq:SI (reg:CC CR6_REGNO)
@ -735,6 +816,10 @@
"TARGET_ALTIVEC || TARGET_VSX"
"")
;; This expansion is triggered during expansion of predicate built-in
;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
;; altivec_expand_predicate_builtin() function when the value of the
;; integer constant first argument equals two (aka __CR6_LT in altivec.h).
(define_expand "cr6_test_for_lt"
[(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (reg:CC CR6_REGNO)
@ -742,6 +827,11 @@
"TARGET_ALTIVEC || TARGET_VSX"
"")
;; This expansion is triggered during expansion of predicate built-in
;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
;; altivec_expand_predicate_builtin() function when the value of the
;; integer constant first argument equals three
;; (aka __CR6_LT_REV in altivec.h).
(define_expand "cr6_test_for_lt_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
(lt:SI (reg:CC CR6_REGNO)

278
gcc/config/rs6000/vsx.md
View File

@ -269,6 +269,10 @@
;; Iterator for ISA 3.0 vector extract/insert of integer vectors
(define_mode_iterator VSX_EXTRACT_I [V16QI V8HI V4SI])
(define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
(V8HI "h")
(V4SI "w")])
;; Mode attribute to give the correct predicate for ISA 3.0 vector extract and
;; insert to validate the operand number.
(define_mode_attr VSX_EXTRACT_PREDICATE [(V16QI "const_0_to_15_operand")
@ -334,6 +338,22 @@
UNSPEC_VSX_VIEXP
UNSPEC_VSX_VTSTDC
UNSPEC_VSX_VEC_INIT
UNSPEC_LXVL
UNSPEC_STXVL
UNSPEC_VCLZLSBB
UNSPEC_VCTZLSBB
UNSPEC_VEXTUBLX
UNSPEC_VEXTUHLX
UNSPEC_VEXTUWLX
UNSPEC_VEXTUBRX
UNSPEC_VEXTUHRX
UNSPEC_VEXTUWRX
UNSPEC_VCMPNEB
UNSPEC_VCMPNEZB
UNSPEC_VCMPNEH
UNSPEC_VCMPNEZH
UNSPEC_VCMPNEW
UNSPEC_VCMPNEZW
])
;; VSX moves
@ -3224,3 +3244,261 @@
"TARGET_P9_VECTOR"
"xvtstdc<VSs> %x0,%x1,%2"
[(set_attr "type" "vecsimple")])
;; ISA 3.0 String Operations Support
;; Compare vectors producing a vector result and a predicate, setting CR6
;; to indicate a combined status. This pattern matches v16qi, v8hi, and
;; v4si modes. It does not match v2df, v4sf, or v2di modes. There's no
;; need to match the v2di mode because that is expanded into v4si.
(define_insn "*vsx_ne_<mode>_p"
[(set (reg:CC CR6_REGNO)
(unspec:CC
[(ne:CC (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v")
(match_operand:VSX_EXTRACT_I 2 "gpc_reg_operand" "v"))]
UNSPEC_PREDICATE))
(set (match_operand:VSX_EXTRACT_I 0 "gpc_reg_operand" "=v")
(ne:VSX_EXTRACT_I (match_dup 1)
(match_dup 2)))]
"TARGET_P9_VECTOR"
"xvcmpne<VSX_EXTRACT_WIDTH>. %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Compare vectors producing a vector result and a predicate, setting CR6
;; to indicate a combined status, for v4sf and v2df operands.
(define_insn "*vsx_ne_<mode>_p"
[(set (reg:CC CR6_REGNO)
(unspec:CC [(ne:CC
(match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
UNSPEC_PREDICATE))
(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
(ne:VSX_F (match_dup 1)
(match_dup 2)))]
"TARGET_P9_VECTOR"
"xvcmpne<VSs>. %x0,%x1,%x2"
[(set_attr "type" "vecsimple")])
(define_insn "*vector_nez_<mode>_p"
[(set (reg:CC CR6_REGNO)
(unspec:CC [(unspec:VI
[(match_operand:VI 1 "gpc_reg_operand" "v")
(match_operand:VI 2 "gpc_reg_operand" "v")]
UNSPEC_NEZ_P)]
UNSPEC_PREDICATE))
(set (match_operand:VI 0 "gpc_reg_operand" "=v")
(unspec:VI [(match_dup 1)
(match_dup 2)]
UNSPEC_NEZ_P))]
"TARGET_P9_VECTOR"
"vcmpnez<VSX_EXTRACT_WIDTH>. %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Load VSX Vector with Length
(define_expand "lxvl"
[(set (match_dup 3)
(match_operand:DI 2 "register_operand"))
(set (match_operand:V16QI 0 "vsx_register_operand")
(unspec:V16QI
[(match_operand:DI 1 "gpc_reg_operand")
(match_dup 3)]
UNSPEC_LXVL))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
operands[3] = gen_reg_rtx (DImode);
})
(define_insn "*lxvl"
[(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
(unspec:V16QI
[(match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand:DI 2 "register_operand" "+r")]
UNSPEC_LXVL))]
"TARGET_P9_VECTOR && TARGET_64BIT"
"sldi %2,%2, 56\; lxvl %x0,%1,%2"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
;; Store VSX Vector with Length
(define_expand "stxvl"
[(set (match_dup 3)
(match_operand:DI 2 "register_operand"))
(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand"))
(unspec:V16QI
[(match_operand:V16QI 0 "vsx_register_operand")
(match_dup 3)]
UNSPEC_STXVL))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
operands[3] = gen_reg_rtx (DImode);
})
(define_insn "*stxvl"
[(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
(unspec:V16QI
[(match_operand:V16QI 0 "vsx_register_operand" "wa")
(match_operand:DI 2 "register_operand" "+r")]
UNSPEC_STXVL))]
"TARGET_P9_VECTOR && TARGET_64BIT"
"sldi %2,%2\;stxvl %x0,%1,%2"
[(set_attr "length" "8")
(set_attr "type" "vecstore")])
;; Vector Compare Not Equal Byte
(define_insn "vcmpneb"
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VCMPNEB))]
"TARGET_P9_VECTOR"
"vcmpneb %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Compare Not Equal or Zero Byte
(define_insn "vcmpnezb"
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
(unspec:V16QI
[(match_operand:V16QI 1 "altivec_register_operand" "v")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VCMPNEZB))]
"TARGET_P9_VECTOR"
"vcmpnezb %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Compare Not Equal Half Word
(define_insn "vcmpneh"
[(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "altivec_register_operand" "v")
(match_operand:V8HI 2 "altivec_register_operand" "v")]
UNSPEC_VCMPNEH))]
"TARGET_P9_VECTOR"
"vcmpneh %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Compare Not Equal or Zero Half Word
(define_insn "vcmpnezh"
[(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "altivec_register_operand" "v")
(match_operand:V8HI 2 "altivec_register_operand" "v")]
UNSPEC_VCMPNEZH))]
"TARGET_P9_VECTOR"
"vcmpnezh %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Compare Not Equal Word
(define_insn "vcmpnew"
[(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
(unspec:V4SI
[(match_operand:V4SI 1 "altivec_register_operand" "v")
(match_operand:V4SI 2 "altivec_register_operand" "v")]
UNSPEC_VCMPNEH))]
"TARGET_P9_VECTOR"
"vcmpnew %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Compare Not Equal Float or Double
(define_insn "vcmpne<VSs>"
[(set (match_operand:<VSI> 0 "vsx_register_operand" "=wa")
(unspec:<VSI>
[(match_operand:VSX_F 1 "vsx_register_operand" "wa")
(match_operand:VSX_F 2 "vsx_register_operand" "wa")]
UNSPEC_VCMPNEH))]
"TARGET_P9_VECTOR"
"xvcmpne<VSs> %x0,%x1,%x2"
[(set_attr "type" "vecsimple")])
;; Vector Compare Not Equal or Zero Word
(define_insn "vcmpnezw"
[(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "altivec_register_operand" "v")
(match_operand:V4SI 2 "altivec_register_operand" "v")]
UNSPEC_VCMPNEZW))]
"TARGET_P9_VECTOR"
"vcmpnezw %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Count Leading Zero Least-Significant Bits Byte
(define_insn "vclzlsbb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:V16QI 1 "altivec_register_operand" "v")]
UNSPEC_VCLZLSBB))]
"TARGET_P9_VECTOR"
"vclzlsbb %0,%1"
[(set_attr "type" "vecsimple")])
;; Vector Count Trailing Zero Least-Significant Bits Byte
(define_insn "vctzlsbb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:V16QI 1 "altivec_register_operand" "v")]
UNSPEC_VCTZLSBB))]
"TARGET_P9_VECTOR"
"vctzlsbb %0,%1"
[(set_attr "type" "vecsimple")])
;; Vector Extract Unsigned Byte Left-Indexed
(define_insn "vextublx"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:SI 1 "register_operand" "r")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VEXTUBLX))]
"TARGET_P9_VECTOR"
"vextublx %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Extract Unsigned Byte Right-Indexed
(define_insn "vextubrx"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:SI 1 "register_operand" "r")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VEXTUBRX))]
"TARGET_P9_VECTOR"
"vextubrx %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Extract Unsigned Half Word Left-Indexed
(define_insn "vextuhlx"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:SI 1 "register_operand" "r")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VEXTUHLX))]
"TARGET_P9_VECTOR"
"vextuhlx %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Extract Unsigned Half Word Right-Indexed
(define_insn "vextuhrx"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:SI 1 "register_operand" "r")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VEXTUHRX))]
"TARGET_P9_VECTOR"
"vextuhrx %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Extract Unsigned Word Left-Indexed
(define_insn "vextuwlx"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:SI 1 "register_operand" "r")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VEXTUWLX))]
"TARGET_P9_VECTOR"
"vextuwlx %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; Vector Extract Unsigned Word Right-Indexed
(define_insn "vextuwrx"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
[(match_operand:SI 1 "register_operand" "r")
(match_operand:V16QI 2 "altivec_register_operand" "v")]
UNSPEC_VEXTUWRX))]
"TARGET_P9_VECTOR"
"vextuwrx %0,%1,%2"
[(set_attr "type" "vecsimple")])

133
gcc/doc/extend.texi
View File

@ -15137,6 +15137,139 @@ The @code{__builtin_dfp_dtstsfi_ov_dd} and
require that the type of the @code{value} argument be
@code{__Decimal64} and @code{__Decimal128} respectively.
The following built-in functions are also available for the PowerPC family
of processors, starting with ISA 3.0 or later
(@option{-mcpu=power9}). These string functions are described
separately in order to group the descriptions closer to the function
prototypes:
@smallexample
int vec_all_nez (vector signed char, vector signed char);
int vec_all_nez (vector unsigned char, vector unsigned char);
int vec_all_nez (vector signed short, vector signed short);
int vec_all_nez (vector unsigned short, vector unsigned short);
int vec_all_nez (vector signed int, vector signed int);
int vec_all_nez (vector unsigned int, vector unsigned int);
int vec_any_eqz (vector signed char, vector signed char);
int vec_any_eqz (vector unsigned char, vector unsigned char);
int vec_any_eqz (vector signed short, vector signed short);
int vec_any_eqz (vector unsigned short, vector unsigned short);
int vec_any_eqz (vector signed int, vector signed int);
int vec_any_eqz (vector unsigned int, vector unsigned int);
vector bool char vec_cmpnez (vector signed char arg1, vector signed char arg2);
vector bool char vec_cmpnez (vector unsigned char arg1, vector unsigned char arg2);
vector bool short vec_cmpnez (vector signed short arg1, vector signed short arg2);
vector bool short vec_cmpnez (vector unsigned short arg1, vector unsigned short arg2);
vector bool int vec_cmpnez (vector signed int arg1, vector signed int arg2);
vector bool int vec_cmpnez (vector unsigned int, vector unsigned int);
signed int vec_cntlz_lsbb (vector signed char);
signed int vec_cntlz_lsbb (vector unsigned char);
signed int vec_cnttz_lsbb (vector signed char);
signed int vec_cnttz_lsbb (vector unsigned char);
vector signed char vec_xl_len (signed char *addr, size_t len);
vector unsigned char vec_xl_len (unsigned char *addr, size_t len);
vector signed int vec_xl_len (signed int *addr, size_t len);
vector unsigned int vec_xl_len (unsigned int *addr, size_t len);
vector signed __int128 vec_xl_len (signed __int128 *addr, size_t len);
vector unsigned __int128 vec_xl_len (unsigned __int128 *addr, size_t len);
vector signed long long vec_xl_len (signed long long *addr, size_t len);
vector unsigned long long vec_xl_len (unsigned long long *addr, size_t len);
vector signed short vec_xl_len (signed short *addr, size_t len);
vector unsigned short vec_xl_len (unsigned short *addr, size_t len);
vector double vec_xl_len (double *addr, size_t len);
vector float vec_xl_len (float *addr, size_t len);
void vec_xst_len (vector signed char data, signed char *addr, size_t len);
void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len);
void vec_xst_len (vector signed int data, signed int *addr, size_t len);
void vec_xst_len (vector unsigned int data, unsigned int *addr, size_t len);
void vec_xst_len (vector unsigned __int128 data, unsigned __int128 *addr, size_t len);
void vec_xst_len (vector signed long long data, signed long long *addr, size_t len);
void vec_xst_len (vector unsigned long long data, unsigned long long *addr, size_t len);
void vec_xst_len (vector signed short data, signed short *addr, size_t len);
void vec_xst_len (vector unsigned short data, unsigned short *addr, size_t len);
void vec_xst_len (vector signed __int128 data, signed __int128 *addr, size_t len);
void vec_xst_len (vector double data, double *addr, size_t len);
void vec_xst_len (vector float data, float *addr, size_t len);
signed char vec_xlx (unsigned int index, vector signed char data);
unsigned char vec_xlx (unsigned int index, vector unsigned char data);
signed short vec_xlx (unsigned int index, vector signed short data);
unsigned short vec_xlx (unsigned int index, vector unsigned short data);
signed int vec_xlx (unsigned int index, vector signed int data);
unsigned int vec_xlx (unsigned int index, vector unsigned int data);
float vec_xlx (unsigned int index, vector float data);
signed char vec_xrx (unsigned int index, vector signed char data);
unsigned char vec_xrx (unsigned int index, vector unsigned char data);
signed short vec_xrx (unsigned int index, vector signed short data);
unsigned short vec_xrx (unsigned int index, vector unsigned short data);
signed int vec_xrx (unsigned int index, vector signed int data);
unsigned int vec_xrx (unsigned int index, vector unsigned int data);
float vec_xrx (unsigned int index, vector float data);
@end smallexample
The @code{vec_all_nez}, @code{vec_any_eqz}, and @code{vec_cmpnez}
perform pairwise comparisons between the elements at the same
positions within their two vector arguments.
The @code{vec_all_nez} function returns a
non-zero value if and only if all pairwise comparisons are not
equal and no element of either vector argument contains a zero.
The @code{vec_any_eqz} function returns a
non-zero value if and only if at least one pairwise comparison is equal
or if at least one element of either vector argument contains a zero.
The @code{vec_cmpnez} function returns a vector of the same type as
its two arguments, within which each element consists of all ones to
denote that either the corresponding elements of the incoming arguments are
not equal or that at least one of the corresponding elements contains
zero. Otherwise, the element of the returned vector contains all zeros.
The @code{vec_cntlz_lsbb} function returns the count of the number of
consecutive leading byte elements (starting from position 0 within the
supplied vector argument) for which the least-significant bit
equals zero. The @code{vec_cnttz_lsbb} function returns the count of
the number of consecutive trailing byte elements (starting from
position 15 and counting backwards within the supplied vector
argument) for which the least-significant bit equals zero.
The @code{vec_xl_len} and @code{vec_xst_len} functions require a
64-bit environment supporting ISA 3.0 or later. The @code{vec_xl_len}
function loads a variable length vector from memory. The
@code{vec_xst_len} function stores a variable length vector to memory.
With both the @code{vec_xl_len} and @code{vec_xst_len} functions, the
@code{addr} argument represents the memory address to or from which
data will be transferred, and the
@code{len} argument represents the number of bytes to be
transferred, as computed by the C expression @code{min((len & 0xff), 16)}.
If this expression's value is not a multiple of the vector element's
size, the behavior of this function is undefined.
In the case that the underlying computer is configured to run in
big-endian mode, the data transfer moves bytes 0 to @code{(len - 1)} of
the corresponding vector. In little-endian mode, the data transfer
moves bytes @code{(16 - len)} to @code{15} of the corresponding
vector. For the load function, any bytes of the result vector that
are not loaded from memory are set to zero.
The value of the @code{addr} argument need not be aligned on a
multiple of the vector's element size.
The @code{vec_xlx} and @code{vec_xrx} functions extract the single
element selected by the @code{index} argument from the vector
represented by the @code{data} argument. The @code{index} argument
always specifies a byte offset, regardless of the size of the vector
element. With @code{vec_xlx}, @code{index} is the offset of the first
byte of the element to be extracted. With @code{vec_xrx}, @code{index}
represents the last byte of the element to be extracted, measured
from the right end of the vector. In other words, the last byte of
the element to be extracted is found at position @code{(15 - index)}.
There is no requirement that @code{index} be a multiple of the vector
element size. However, if the size of the vector element added to
@code{index} is greater than 15, the content of the returned value is
undefined.
The following built-in functions are available for the PowerPC family
of processors when hardware decimal floating point
(@option{-mhard-dfp}) is available:

114
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,117 @@
2016-10-18 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/vsu/vec-all-ne-0.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-1.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-10.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-11.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-12.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-13.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-14.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-2.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-3.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-4.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-5.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-6.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-7.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-8.c: New test.
* gcc.target/powerpc/vsu/vec-all-ne-9.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-1.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-2.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-3.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-4.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-5.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-6.c: New test.
* gcc.target/powerpc/vsu/vec-all-nez-7.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-0.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-1.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-10.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-11.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-12.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-13.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-14.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-2.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-3.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-4.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-5.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-6.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-7.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-8.c: New test.
* gcc.target/powerpc/vsu/vec-any-eq-9.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-1.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-2.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-3.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-4.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-5.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-6.c: New test.
* gcc.target/powerpc/vsu/vec-any-eqz-7.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-0.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-1.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-2.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-3.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-4.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-5.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-6.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-8.c: New test.
* gcc.target/powerpc/vsu/vec-cmpne-9.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-1.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-2.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-3.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-4.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-5.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-6.c: New test.
* gcc.target/powerpc/vsu/vec-cmpnez-7.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: New test.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: New test.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-0.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-1.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-10.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-11.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-12.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-13.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-2.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-3.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-4.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-5.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-6.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-7.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-8.c: New test.
* gcc.target/powerpc/vsu/vec-xl-len-9.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-0.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-1.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-2.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-3.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-4.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-5.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-6.c: New test.
* gcc.target/powerpc/vsu/vec-xlx-7.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-0.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-1.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-2.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-3.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-4.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-5.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-6.c: New test.
* gcc.target/powerpc/vsu/vec-xrx-7.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-0.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-1.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-10.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-11.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-12.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-13.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-2.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-3.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-4.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-5.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-6.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-7.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-8.c: New test.
* gcc.target/powerpc/vsu/vec-xst-len-9.c: New test.
* gcc.target/powerpc/vsu/vsu.exp: New file.
2016-10-18 Uros Bizjak <ubizjak@gmail.com>
PR target/77991

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector bool char *arg1_p, vector bool char *arg2_p)
{
vector bool char arg_1 = *arg1_p;
vector bool char arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector signed char *arg1_p, vector signed char *arg2_p)
{
vector signed char arg_1 = *arg1_p;
vector signed char arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-10.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector unsigned long long *arg1_p,
vector unsigned long long *arg2_p)
{
vector unsigned long long arg_1 = *arg1_p;
vector unsigned long long arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-11.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector pixel *arg1_p, vector pixel *arg2_p)
{
vector pixel arg_1 = *arg1_p;
vector pixel arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-12.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector bool short *arg1_p, vector bool short *arg2_p)
{
vector bool short arg_1 = *arg1_p;
vector bool short arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-13.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector bool int *arg1_p, vector bool int *arg2_p)
{
vector bool int arg_1 = *arg1_p;
vector bool int arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-14.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector bool long long *arg1_p, vector bool long long *arg2_p)
{
vector bool long long arg_1 = *arg1_p;
vector bool long long arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector unsigned char *arg1_p, vector unsigned char *arg2_p)
{
vector unsigned char arg_1 = *arg1_p;
vector unsigned char arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector signed short *arg1_p, vector signed short *arg2_p)
{
vector signed short arg_1 = *arg1_p;
vector signed short arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector unsigned short *arg1_p,
vector unsigned short *arg2_p)
{
vector unsigned short arg_1 = *arg1_p;
vector unsigned short arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector signed int *arg1_p, vector signed int *arg2_p)
{
vector signed int arg_1 = *arg1_p;
vector signed int arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector float *arg1_p, vector float *arg2_p)
{
vector float arg_1 = *arg1_p;
vector float arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "xvcmpnesp." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-8.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector double *arg1_p, vector double *arg2_p)
{
vector double arg_1 = *arg1_p;
vector double arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "xvcmpnedp." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-9.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal (vector long long *arg1_p, vector long long *arg2_p)
{
vector long long arg_1 = *arg1_p;
vector long long arg_2 = *arg2_p;
return vec_all_ne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal_and_not_zero (vector signed char *arg1_p,
vector signed char *arg2_p)
{
vector signed char arg_1 = *arg1_p;
vector signed char arg_2 = *arg2_p;
return vec_all_nez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezb." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal_and_not_zero (vector unsigned char *arg1_p,
vector unsigned char *arg2_p)
{
vector unsigned char arg_1 = *arg1_p;
vector unsigned char arg_2 = *arg2_p;
return vec_all_nez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezb." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal_and_not_zero (vector signed short *arg1_p,
vector signed short *arg2_p)
{
vector signed short arg_1 = *arg1_p;
vector signed short arg_2 = *arg2_p;
return vec_all_nez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezh." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal_and_not_zero (vector unsigned short *arg1_p,
vector unsigned short *arg2_p)
{
vector unsigned short arg_1 = *arg1_p;
vector unsigned short arg_2 = *arg2_p;
return vec_all_nez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezh." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal_and_not_zero (vector signed int *arg1_p,
vector signed int *arg2_p)
{
vector signed int arg_1 = *arg1_p;
vector signed int arg_2 = *arg2_p;
return vec_all_nez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezw." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_all_not_equal_and_not_zero (vector unsigned int *arg1_p,
vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return vec_all_nez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezw." } } */

16
gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power8" } */
#include <altivec.h>
int
test_all_not_equal_and_not_zero (vector unsigned short *arg1_p,
vector unsigned short *arg2_p)
{
vector unsigned short arg_1 = *arg1_p;
vector unsigned short arg_2 = *arg2_p;
return __builtin_vec_vcmpnez_p (__CR6_LT, arg_1, arg_2); /* { dg-error "Builtin function __builtin_altivec_vcmpnezh_p requires" } */
}

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector bool char *arg1_p, vector bool char *arg2_p)
{
vector bool char arg_1 = *arg1_p;
vector bool char arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector signed char *arg1_p, vector signed char *arg2_p)
{
vector signed char arg_1 = *arg1_p;
vector signed char arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector unsigned long long *arg1_p,
vector unsigned long long *arg2_p)
{
vector unsigned long long arg_1 = *arg1_p;
vector unsigned long long arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-11.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector pixel *arg1_p, vector pixel *arg2_p)
{
vector pixel arg_1 = *arg1_p;
vector pixel arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-12.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector bool short *arg1_p, vector bool short *arg2_p)
{
vector bool short arg_1 = *arg1_p;
vector bool short arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-13.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector bool int *arg1_p, vector bool int *arg2_p)
{
vector bool int arg_1 = *arg1_p;
vector bool int arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector bool long long *arg1_p, vector bool long long *arg2_p)
{
vector bool long long arg_1 = *arg1_p;
vector bool long long arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector unsigned char *arg1_p, vector unsigned char *arg2_p)
{
vector unsigned char arg_1 = *arg1_p;
vector unsigned char arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector signed short *arg1_p, vector signed short *arg2_p)
{
vector signed short arg_1 = *arg1_p;
vector signed short arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector unsigned short *arg1_p,
vector unsigned short *arg2_p)
{
vector unsigned short arg_1 = *arg1_p;
vector unsigned short arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector signed int *arg1_p, vector signed int *arg2_p)
{
vector signed int arg_1 = *arg1_p;
vector signed int arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector float *arg1_p, vector float *arg2_p)
{
vector float arg_1 = *arg1_p;
vector float arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "xvcmpnesp." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector double *arg1_p, vector double *arg2_p)
{
vector double arg_1 = *arg1_p;
vector double arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "xvcmpnedp." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal (vector long long *arg1_p, vector long long *arg2_p)
{
vector long long arg_1 = *arg1_p;
vector long long arg_2 = *arg2_p;
return vec_any_eq (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal_or_zero (vector signed char *arg1_p, vector signed char *arg2_p)
{
vector signed char arg_1 = *arg1_p;
vector signed char arg_2 = *arg2_p;
return vec_any_eqz (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezb." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal_or_zero (vector unsigned char *arg1_p,
vector unsigned char *arg2_p)
{
vector unsigned char arg_1 = *arg1_p;
vector unsigned char arg_2 = *arg2_p;
return vec_any_eqz (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezb." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal_or_zero (vector signed short *arg1_p,
vector signed short *arg2_p)
{
vector signed short arg_1 = *arg1_p;
vector signed short arg_2 = *arg2_p;
return vec_any_eqz (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezh." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal_or_zero (vector unsigned short *arg1_p,
vector unsigned short *arg2_p)
{
vector unsigned short arg_1 = *arg1_p;
vector unsigned short arg_2 = *arg2_p;
return vec_any_eqz (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezh." } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal_or_zero (vector signed int *arg1_p, vector signed int *arg2_p)
{
vector signed int arg_1 = *arg1_p;
vector signed int arg_2 = *arg2_p;
return vec_any_eqz (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezw." } } */

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
test_any_equal_or_zero (vector unsigned int *arg1_p,
vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return vec_any_eqz (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezw." } } */

15
gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power8" } */
#include <altivec.h>
int
test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return __builtin_vec_vcmpnez_p (__CR6_LT_REV, arg_1, arg_2); /* { dg-error "Builtin function __builtin_altivec_vcmpnezw_p requires" } */
}

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool char
fetch_data (vector bool char *arg1_p, vector bool char *arg2_p)
{
vector bool char arg_1 = *arg1_p;
vector bool char arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool char
fetch_data (vector signed char *arg1_p, vector signed char *arg2_p)
{
vector signed char arg_1 = *arg1_p;
vector signed char arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool char
fetch_data (vector unsigned char *arg1_p, vector unsigned char *arg2_p)
{
vector unsigned char arg_1 = *arg1_p;
vector unsigned char arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneb" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool short
fetch_data (vector signed short *arg1_p, vector signed short *arg2_p)
{
vector signed short arg_1 = *arg1_p;
vector signed short arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool short
fetch_data (vector unsigned short *arg1_p, vector unsigned short *arg2_p)
{
vector unsigned short arg_1 = *arg1_p;
vector unsigned short arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpneh" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool int
fetch_data (vector signed int *arg1_p, vector signed int *arg2_p)
{
vector signed int arg_1 = *arg1_p;
vector signed int arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool int
fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnew" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-8.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool int
fetch_data (vector float *arg1_p, vector float *arg2_p)
{
vector float arg_1 = *arg1_p;
vector float arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "xvcmpnesp" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-9.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool long long
fetch_data (vector double *arg1_p, vector double *arg2_p)
{
vector double arg_1 = *arg1_p;
vector double arg_2 = *arg2_p;
return vec_cmpne (arg_1, arg_2);
}
/* { dg-final { scan-assembler "xvcmpnedp" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool char
fetch_data (vector signed char *arg1_p, vector signed char *arg2_p)
{
vector signed char arg_1 = *arg1_p;
vector signed char arg_2 = *arg2_p;
return vec_cmpnez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezb" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool char
fetch_data (vector unsigned char *arg1_p, vector unsigned char *arg2_p)
{
vector unsigned char arg_1 = *arg1_p;
vector unsigned char arg_2 = *arg2_p;
return vec_cmpnez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezb" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool short
fetch_data (vector signed short *arg1_p, vector signed short *arg2_p)
{
vector signed short arg_1 = *arg1_p;
vector signed short arg_2 = *arg2_p;
return vec_cmpnez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezh" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool short
fetch_data (vector unsigned short *arg1_p, vector unsigned short *arg2_p)
{
vector unsigned short arg_1 = *arg1_p;
vector unsigned short arg_2 = *arg2_p;
return vec_cmpnez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezh" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool int
fetch_data (vector signed int *arg1_p, vector signed int *arg2_p)
{
vector signed int arg_1 = *arg1_p;
vector signed int arg_2 = *arg2_p;
return vec_cmpnez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezw" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
vector bool int
fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return vec_cmpnez (arg_1, arg_2);
}
/* { dg-final { scan-assembler "vcmpnezw" } } */

15
gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power8" } */
#include <altivec.h>
vector bool int
fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p)
{
vector unsigned int arg_1 = *arg1_p;
vector unsigned int arg_2 = *arg2_p;
return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "Builtin function __builtin_altivec_vcmpnezw requires the -mcpu=power9 option" } */
}

16
gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
count_leading_zero_byte_bits (vector signed char *arg1_p)
{
vector signed char arg_1 = *arg1_p;
return vec_cntlz_lsbb (arg_1);
}
/* { dg-final { scan-assembler "vclzlsbb" } } */

16
gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
count_leading_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
return vec_cntlz_lsbb (arg_1);
}
/* { dg-final { scan-assembler "vclzlsbb" } } */

14
gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power8" } */
#include <altivec.h>
int
count_leading_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "Builtin function __builtin_altivec_vclzlsbb requires the -mcpu=power9 option" } */
}

16
gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
count_trailing_zero_byte_bits (vector signed char *arg1_p)
{
vector signed char arg_1 = *arg1_p;
return vec_cnttz_lsbb (arg_1);
}
/* { dg-final { scan-assembler "vctzlsbb" } } */

16
gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <altivec.h>
int
count_trailing_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
return vec_cnttz_lsbb (arg_1);
}
/* { dg-final { scan-assembler "vctzlsbb" } } */

14
gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power8" } */
#include <altivec.h>
int
count_trailing_zero_byte_bits (vector unsigned char *arg1_p)
{
vector unsigned char arg_1 = *arg1_p;
return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "Builtin function __builtin_altivec_vctzlsbb requires the -mcpu=power9 option" } */
}

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector signed char
fetch_data (signed char *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector unsigned char
fetch_data (unsigned char *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector double
fetch_data (double *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector float
fetch_data (float *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

16
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c Normal file
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@ -0,0 +1,16 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power8" } */
/* The vec_xl_len() function is not available on power8 configurations. */
#include <stddef.h>
#include <altivec.h>
__vector float
fetch_data (float *address, size_t length)
{
return __builtin_vec_lxvl (address, length); /* { dg-error "Builtin function __builtin_vsx_lxvl requires" } */
}

18
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target ilp32 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
/* This test only runs on 32-bit configurations, where a compiler
error should be issued because this built-in function is not
available on 32-bit configurations. */
__vector float
fetch_data (float *address, size_t length)
{
return __builtin_vec_lxvl (address, length); /* { dg-error "Builtin function __builtin_vec_lxvl not supported in this compiler configuration" } */
}

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector signed int
fetch_data (signed int *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector unsigned int
fetch_data (unsigned int *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector signed __int128
fetch_data (signed __int128 *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector unsigned __int128
fetch_data (unsigned __int128 *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector signed long long
fetch_data (signed long long *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector unsigned long long
fetch_data (unsigned long long *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector signed short
fetch_data (signed short *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
__vector unsigned short
fetch_data (unsigned short *address, size_t length)
{
return vec_xl_len (address, length);
}
/* { dg-final { scan-assembler "sldi" } } */
/* { dg-final { scan-assembler "lxvl" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-0.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
signed char
fetch_data (unsigned int offset, vector signed char *datap)
{
vector signed char data = *datap;
return vec_xlx (offset, data);
}
/* { dg-final { scan-assembler "vextublx" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-1.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
unsigned char
fetch_data (unsigned int offset, vector unsigned char *datap)
{
vector unsigned char data = *datap;
return vec_xlx (offset, data);
}
/* { dg-final { scan-assembler "vextublx" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-2.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
signed short
fetch_data (unsigned int offset, vector signed short *datap)
{
vector signed short data = *datap;
return vec_xlx (offset, data);
}
/* { dg-final { scan-assembler "vextuhlx" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-3.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
unsigned short
fetch_data (unsigned int offset, vector unsigned short *datap)
{
vector unsigned short data = *datap;
return vec_xlx (offset, data);
}
/* { dg-final { scan-assembler "vextuhlx" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-4.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
signed int
fetch_data (unsigned int offset, vector signed int *datap)
{
vector signed int data = *datap;
return vec_xlx (offset, data);
}
/* { dg-final { scan-assembler "vextuwlx" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-5.c Normal file
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@ -0,0 +1,17 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
unsigned int
fetch_data (unsigned int offset, vector unsigned int *datap)
{
vector unsigned int data = *datap;
return vec_xlx (offset, data);
}
/* { dg-final { scan-assembler "vextuwlx" } } */

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-6.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
float
fetch_data (unsigned int offset, vector float *datap)
{
vector float data = *datap;
return vec_xlx (offset, data);
}
/* { dg-final { scan-assembler "vextuwlx" } } */

15
gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-7.c Normal file
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@ -0,0 +1,15 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power8" } */
#include <stddef.h>
#include <altivec.h>
signed int
fetch_data (unsigned int offset, vector signed int *datap)
{
vector signed int data = *datap;
return __builtin_vec_vextulx (offset, data); /* { dg-error "Builtin function __builtin_altivec_vextuwlx requires" } */
}

17
gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-0.c Normal file
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/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mcpu=power9" } */
#include <stddef.h>
#include <altivec.h>
signed char
fetch_data (unsigned int offset, vector signed char *datap)
{
vector signed char data = *datap;
return vec_xrx (offset, data);
}
/* { dg-final { scan-assembler "vextubrx" } } */

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