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PR target/pr42542 

2010-01-13  Steve Ellcey  <sje@cup.hp.com>

	PR target/pr42542
	* config/ia64/ia64.c (ia64_expand_vecint_compare): Convert GTU to GT
	for V2SI by subtracting (-(INT MAX) - 1) from both operands to make
	them signed.

From-SVN: r155870
This commit is contained in:
Steve Ellcey 2010-01-13 22:16:25 +00:00 committed by Steve Ellcey
parent a5859aaf07
commit 9540f5ef92
2 changed files with 17 additions and 17 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2010-01-13 Steve Ellcey <sje@cup.hp.com>
PR target/pr42542
* config/ia64/ia64.c (ia64_expand_vecint_compare): Convert GTU to GT
for V2SI by subtracting (-(INT MAX) - 1) from both operands to make
them signed.
2010-01-13 Bernd Schmidt <bernd.schmidt@analog.com>
* config/bfin/libgcc-bfin.ver: Regenerate based on current

27
gcc/config/ia64/ia64.c
View File

@ -1733,25 +1733,18 @@ ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
{
rtx t1, t2, mask;
/* Perform a parallel modulo subtraction. */
t1 = gen_reg_rtx (V2SImode);
emit_insn (gen_subv2si3 (t1, op0, op1));
/* Extract the original sign bit of op0. */
mask = GEN_INT (-0x80000000);
/* Subtract (-(INT MAX) - 1) from both operands to make
them signed. */
mask = GEN_INT (0x80000000);
mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
mask = force_reg (V2SImode, mask);
t2 = gen_reg_rtx (V2SImode);
emit_insn (gen_andv2si3 (t2, op0, mask));
/* XOR it back into the result of the subtraction. This results
in the sign bit set iff we saw unsigned underflow. */
x = gen_reg_rtx (V2SImode);
emit_insn (gen_xorv2si3 (x, t1, t2));
mask = force_reg (mode, mask);
t1 = gen_reg_rtx (mode);
emit_insn (gen_subv2si3 (t1, op0, mask));
t2 = gen_reg_rtx (mode);
emit_insn (gen_subv2si3 (t2, op1, mask));
op0 = t1;
op1 = t2;
code = GT;
op0 = x;
op1 = CONST0_RTX (mode);
}
break;