re PR target/54051 (Invalid alignment specifier generated for vld3_lane_* and vld3_dup_* intrinsics.)

Fix PR target/54051


2012-07-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/54051
	* config/arm/arm.c (arm_print_operand_address): Remove superfluous
	printing of 0.
	* config/arm/neon.md ("neon_vld3_lane<mode>":VD): Remove alignment
	specifier.
	("neon_vld3_lane<mode>":VMQ): Likewise.
	("neon_vld3_dup<mode>":VDX): Likewise.
	("neon_vst3_lane<mode>":VD): Likewise.
	("neon_vst3_lane<mode>":VMQ): Likewise.


2012-07-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/54051
	* gcc.target/arm/pr54051.c: New.
	* gcc.target/arm/vfp-1.c: Adjust test.

From-SVN: r189808

gcc/ChangeLog

@@ -1,6 +1,18 @@
+2012-07-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	PR target/54051
+	* config/arm/arm.c (arm_print_operand_address): Remove superfluous
+	printing of 0.
+	* config/arm/neon.md ("neon_vld3_lane<mode>":VD): Remove alignment
+	specifier.
+	("neon_vld3_lane<mode>":VMQ): Likewise.
+	("neon_vld3_dup<mode>":VDX): Likewise.
+	("neon_vst3_lane<mode>":VD): Likewise.
+	("neon_vst3_lane<mode>":VMQ): Likewise.
+
 2012-07-24  Roland McGrath  <mcgrathr@google.com>
 
-	* arm.c (arm_get_frame_offsets): Don't use fixed regs for 
+	* arm.c (arm_get_frame_offsets): Don't use fixed regs for
 	stack alignment padding.
 
 2012-07-24  Uros Bizjak  <ubizjak@gmail.com>

gcc/config/arm/arm.c

@@ -17420,7 +17420,7 @@ arm_print_operand_address (FILE *stream, rtx x)
       int is_minus = GET_CODE (x) == MINUS;
 
       if (GET_CODE (x) == REG)
-	asm_fprintf (stream, "[%r, #0]", REGNO (x));
+	asm_fprintf (stream, "[%r]", REGNO (x));
       else if (GET_CODE (x) == PLUS || is_minus)
 	{
 	  rtx base = XEXP (x, 0);

gcc/config/arm/neon.md

@@ -4806,7 +4806,7 @@
   ops[2] = gen_rtx_REG (DImode, regno + 4);
   ops[3] = operands[1];
   ops[4] = operands[3];
-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3",
                    ops);
   return "";
 }
@@ -4838,7 +4838,7 @@
   ops[2] = gen_rtx_REG (DImode, regno + 8);
   ops[3] = operands[1];
   ops[4] = GEN_INT (lane);
-  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
+  output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3",
                    ops);
   return "";
 }
@@ -4860,7 +4860,7 @@
       ops[1] = gen_rtx_REG (DImode, regno + 2);
       ops[2] = gen_rtx_REG (DImode, regno + 4);
       ops[3] = operands[1];
-      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
+      output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %3", ops);
       return "";
     }
   else
@@ -4978,7 +4978,7 @@
   ops[2] = gen_rtx_REG (DImode, regno + 2);
   ops[3] = gen_rtx_REG (DImode, regno + 4);
   ops[4] = operands[2];
-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0",
                    ops);
   return "";
 }
@@ -5010,7 +5010,7 @@
   ops[2] = gen_rtx_REG (DImode, regno + 4);
   ops[3] = gen_rtx_REG (DImode, regno + 8);
   ops[4] = GEN_INT (lane);
-  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
+  output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0",
                    ops);
   return "";
 }

gcc/testsuite/ChangeLog

@@ -1,3 +1,9 @@
+2012-07-24  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	PR target/54051
+	* gcc.target/arm/pr54051.c: New.
+	* gcc.target/arm/vfp-1.c: Adjust test.
+
 2012-07-24  Julian Brown  <julian@codesourcery.com>
 
 	* lib/target-supports.exp (check_effective_target_arm_hf_eabi): New.

gcc/testsuite/gcc.target/arm/pr54051.c

@@ -0,0 +1,20 @@
+/* { dg-do assemble }  */
+/* { dg-require-effective-target arm_neon }  */
+/* { dg-options "-O2" }  */
+/* { dg-add-options arm_neon }  */
+
+#include <arm_neon.h>
+
+int32_t a __attribute__ ((aligned (64)));
+
+int32x2x3_t test (void)
+{
+  return vld3_dup_s32 (&a);
+}
+
+int32x2x3_t test1 (void)
+{
+  int32x2x3_t res ;
+  return vld3_lane_s32 (&a, res, 1);
+}
+

gcc/testsuite/gcc.target/arm/vfp-1.c

@@ -129,7 +129,7 @@ void test_ldst (float f[], double d[]) {
   /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
   /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
   /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
-  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */
+  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */
   f[256] = f[255] + f[-255];
 
   /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */