git
/
gcc
mirror of git://gcc.gnu.org/git/gcc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[AArch64][9/10] ARMv8.2-A FP16 three operands scalar intrinsics 

gcc/
	* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
	* config/aarch64/aarch64.md (fma, fnma): Support HF.
	* config/aarch64/arm_fp16.h (vfmah_f16, vfmsh_f16): New.

From-SVN: r238724
This commit is contained in:
Jiong Wang 2016-07-25 16:13:22 +00:00 committed by Jiong Wang
parent 68ad28c34a
commit 9a594ad6ef
4 changed files with 33 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2016-07-25 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64.md (fma, fnma): Support HF.
* config/aarch64/arm_fp16.h (vfmah_f16, vfmsh_f16): New.
2016-07-25 Jiong Wang <jiong.wang@arm.com> 2016-07-25 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Register new builtins. * config/aarch64/aarch64-simd-builtins.def: Register new builtins.

2
gcc/config/aarch64/aarch64-simd-builtins.def
View File

@ -422,8 +422,10 @@
/* Implemented by fma<mode>4. */ /* Implemented by fma<mode>4. */
BUILTIN_VHSDF (TERNOP, fma, 4) BUILTIN_VHSDF (TERNOP, fma, 4)
VAR1 (TERNOP, fma, 4, hf)
/* Implemented by fnma<mode>4. */ /* Implemented by fnma<mode>4. */
BUILTIN_VHSDF (TERNOP, fnma, 4) BUILTIN_VHSDF (TERNOP, fnma, 4)
VAR1 (TERNOP, fnma, 4, hf)
/* Implemented by aarch64_simd_bsl<mode>. */ /* Implemented by aarch64_simd_bsl<mode>. */
BUILTIN_VDQQH (BSL_P, simd_bsl, 0) BUILTIN_VDQQH (BSL_P, simd_bsl, 0)

21
gcc/config/aarch64/aarch64.md
View File

@ -4492,23 +4492,24 @@
;; fma - no throw ;; fma - no throw
(define_insn "fma<mode>4" (define_insn "fma<mode>4"
[(set (match_operand:GPF 0 "register_operand" "=w") [(set (match_operand:GPF_F16 0 "register_operand" "=w")
(fma:GPF (match_operand:GPF 1 "register_operand" "w") (fma:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")
(match_operand:GPF 2 "register_operand" "w") (match_operand:GPF_F16 2 "register_operand" "w")
(match_operand:GPF 3 "register_operand" "w")))] (match_operand:GPF_F16 3 "register_operand" "w")))]
"TARGET_FLOAT" "TARGET_FLOAT"
"fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3" "fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3"
[(set_attr "type" "fmac<s>")] [(set_attr "type" "fmac<stype>")]
) )
(define_insn "fnma<mode>4" (define_insn "fnma<mode>4"
[(set (match_operand:GPF 0 "register_operand" "=w") [(set (match_operand:GPF_F16 0 "register_operand" "=w")
(fma:GPF (neg:GPF (match_operand:GPF 1 "register_operand" "w")) (fma:GPF_F16
(match_operand:GPF 2 "register_operand" "w") (neg:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w"))
(match_operand:GPF 3 "register_operand" "w")))] (match_operand:GPF_F16 2 "register_operand" "w")
(match_operand:GPF_F16 3 "register_operand" "w")))]
"TARGET_FLOAT" "TARGET_FLOAT"
"fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3" "fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3"
[(set_attr "type" "fmac<s>")] [(set_attr "type" "fmac<stype>")]
) )
(define_insn "fms<mode>4" (define_insn "fms<mode>4"

14
gcc/config/aarch64/arm_fp16.h
View File

@ -560,6 +560,20 @@ vsubh_f16 (float16_t __a, float16_t __b)
return __a - __b; return __a - __b;
} }
/* ARMv8.2-A FP16 three operands scalar intrinsics. */
__extension__ static __inline float16_t __attribute__ ((__always_inline__))
vfmah_f16 (float16_t __a, float16_t __b, float16_t __c)
{
return __builtin_aarch64_fmahf (__b, __c, __a);
}
__extension__ static __inline float16_t __attribute__ ((__always_inline__))
vfmsh_f16 (float16_t __a, float16_t __b, float16_t __c)
{
return __builtin_aarch64_fnmahf (__b, __c, __a);
}
#pragma GCC pop_options #pragma GCC pop_options
#endif #endif