mirror of git://gcc.gnu.org/git/gcc.git
re PR target/58779 (wrong code at -O1 on x86_64-linux-gnu)
PR target/58779 * config/i386/i386.c (put_condition_code) <case GTU, case LEU>: Remove CCCmode handling. <case LTU>: Return 'c' suffix for CCCmode. <case GEU>: Return 'nc' suffix for CCCmode. (ix86_cc_mode) <case GTU, case LEU>: Do not generate overflow checks. * config/i386/i386.md (*sub<mode>3_cconly_overflow): Remove. (*sub<mode>3_cc_overflow): Ditto. (*subsi3_zext_cc_overflow): Ditto. testsuite/ChangeLog: PR target/58779 * gcc.target/i386/pr30315.c: Remove MINUSCC, DECCC, MINUSCCONLY and MINUSCCZEXT defines. Update scan-assembler dg directive. * gcc.dg/torture/pr58779.c: New test. From-SVN: r203935
This commit is contained in:
Uros Bizjak
parent
fb61ee69c3
commit
9ae93484ed
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@ -1,3 +1,15 @@
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2013-10-22 Uros Bizjak <ubizjak@gmail.com>
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PR target/58779
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* config/i386/i386.c (put_condition_code) <case GTU, case LEU>:
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Remove CCCmode handling.
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<case LTU>: Return 'c' suffix for CCCmode.
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<case GEU>: Return 'nc' suffix for CCCmode.
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(ix86_cc_mode) <case GTU, case LEU>: Do not generate overflow checks.
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* config/i386/i386.md (*sub<mode>3_cconly_overflow): Remove.
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(*sub<mode>3_cc_overflow): Ditto.
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(*subsi3_zext_cc_overflow): Ditto.
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2013-10-22 Steve Ellcey <sellcey@mips.com>
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* config/mips/mips.c (mips_rtx_costs): Fix cost estimate for nor
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@ -14103,8 +14103,6 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse,
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Those same assemblers have the same but opposite lossage on cmov. */
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if (mode == CCmode)
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suffix = fp ? "nbe" : "a";
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else if (mode == CCCmode)
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suffix = "b";
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else
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gcc_unreachable ();
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break;
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@ -14126,8 +14124,12 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse,
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}
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break;
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case LTU:
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gcc_assert (mode == CCmode || mode == CCCmode);
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suffix = "b";
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if (mode == CCmode)
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suffix = "b";
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else if (mode == CCCmode)
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suffix = "c";
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else
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gcc_unreachable ();
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break;
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case GE:
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switch (mode)
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@ -14147,20 +14149,20 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse,
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}
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break;
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case GEU:
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/* ??? As above. */
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gcc_assert (mode == CCmode || mode == CCCmode);
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suffix = fp ? "nb" : "ae";
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if (mode == CCmode)
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suffix = fp ? "nb" : "ae";
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else if (mode == CCCmode)
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suffix = "nc";
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else
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gcc_unreachable ();
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break;
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case LE:
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gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
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suffix = "le";
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break;
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case LEU:
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/* ??? As above. */
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if (mode == CCmode)
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suffix = "be";
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else if (mode == CCCmode)
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suffix = fp ? "nb" : "ae";
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else
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gcc_unreachable ();
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break;
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@ -18862,12 +18864,7 @@ ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
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return CCmode;
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case GTU: /* CF=0 & ZF=0 */
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case LEU: /* CF=1 | ZF=1 */
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/* Detect overflow checks. They need just the carry flag. */
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if (GET_CODE (op0) == MINUS
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&& rtx_equal_p (op1, XEXP (op0, 0)))
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return CCCmode;
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else
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return CCmode;
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return CCmode;
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/* Codes possibly doable only with sign flag when
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comparing against zero. */
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case GE: /* SF=OF or SF=0 */
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@ -6489,7 +6489,7 @@
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(set_attr "use_carry" "1")
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(set_attr "mode" "<MODE>")])
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;; Overflow setting add and subtract instructions
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;; Overflow setting add instructions
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(define_insn "*add<mode>3_cconly_overflow"
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[(set (reg:CCC FLAGS_REG)
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@ -6504,43 +6504,31 @@
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*sub<mode>3_cconly_overflow"
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(define_insn "*add<mode>3_cc_overflow"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(minus:SWI
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(match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
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(match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
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(match_dup 0)))]
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""
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"cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
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[(set_attr "type" "icmp")
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(set_attr "mode" "<MODE>")])
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(define_insn "*<plusminus_insn><mode>3_cc_overflow"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(plusminus:SWI
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(match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
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(plus:SWI
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(match_operand:SWI 1 "nonimmediate_operand" "%0,0")
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(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
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(match_dup 1)))
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(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
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(plusminus:SWI (match_dup 1) (match_dup 2)))]
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"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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"<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
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(plus:SWI (match_dup 1) (match_dup 2)))]
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"ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
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"add{<imodesuffix>}\t{%2, %0|%0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "<MODE>")])
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(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
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(define_insn "*addsi3_zext_cc_overflow"
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[(set (reg:CCC FLAGS_REG)
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(compare:CCC
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(plusminus:SI
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(match_operand:SI 1 "nonimmediate_operand" "<comm>0")
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(plus:SI
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(match_operand:SI 1 "nonimmediate_operand" "%0")
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(match_operand:SI 2 "x86_64_general_operand" "rme"))
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(match_dup 1)))
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(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
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"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
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"<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
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(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
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"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
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"add{l}\t{%2, %k0|%k0, %2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "SI")])
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@ -1,3 +1,10 @@
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2013-10-22 Uros Bizjak <ubizjak@gmail.com>
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PR target/58779
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* gcc.target/i386/pr30315.c: Remove MINUSCC, DECCC, MINUSCCONLY
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and MINUSCCZEXT defines. Update scan-assembler dg directive.
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* gcc.dg/torture/pr58779.c: New test.
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2013-10-22 Steve Ellcey <sellcey@mips.com>
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* gcc.target/mips/nor.c: New.
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@ -27,8 +34,7 @@
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2013-10-21 Vidya Praveen <vidyapraveen@arm.com>
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* gcc.dg/20050922-1.c: Remove stdlib.h and declare abort().
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* gcc.dg/20050922-1.c: Remove stdlib.h and declare abort() and
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exit().
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* gcc.dg/20050922-1.c: Remove stdlib.h and declare abort() and exit().
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2013-10-21 Richard Biener <rguenther@suse.de>
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@ -228,8 +234,8 @@
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2013-10-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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* gcc.dg/torture/pr58670.c (ASM_STR) [__i386__ || __x86_64__]: Use
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btsl.
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* gcc.dg/torture/pr58670.c (ASM_STR) [__i386__ || __x86_64__]:
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Use btsl.
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2013-10-14 Eric Botcazou <ebotcazou@adacore.com>
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@ -0,0 +1,12 @@
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/* { dg-do run } */
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int a, c;
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int main ()
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{
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int e = -1;
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short d = (c <= 0) ^ e;
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if ((unsigned int) a - (a || d) <= (unsigned int) a)
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__builtin_abort ();
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return 0;
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}
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@ -1,6 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-final { scan-assembler-times "cmp" 4 } } */
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/* { dg-final { scan-assembler-not "cmp" } } */
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extern void abort (void);
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int c;
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@ -34,39 +34,10 @@ void pluscconly##t##C (T a, T b) \
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}
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#define PLUSCCONLY(T, t) PLUSCCONLY1(T, t, a) PLUSCCONLY1(T, t, b)
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#define MINUSCC(T, t) \
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T minuscc##t (T a, T b) \
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{ \
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T difference = a - b; \
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if (difference > a) \
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abort (); \
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return difference; \
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}
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#define DECCC(T, t) \
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T deccc##t (T a, T b) \
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{ \
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T difference = a - b; \
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if (difference > a) \
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c --; \
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return difference; \
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}
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#define MINUSCCONLY(T, t) \
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void minuscconly##t (T a, T b) \
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{ \
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T difference = a - b; \
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if (difference > a) \
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abort (); \
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}
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#define TEST(T, t) \
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PLUSCC(T, t) \
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PLUSCCONLY(T, t) \
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INCCC(T, t) \
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MINUSCC(T, t) \
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MINUSCCONLY(T, t) \
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DECCC(T, t)
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INCCC(T, t)
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TEST (unsigned long, l)
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TEST (unsigned int, i)
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@ -84,14 +55,3 @@ unsigned long pluscczext##C (unsigned int a, unsigned int b) \
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PLUSCCZEXT(a)
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PLUSCCZEXT(b)
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#define MINUSCCZEXT \
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unsigned long minuscczext (unsigned int a, unsigned int b) \
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{ \
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unsigned int difference = a - b; \
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if (difference > a) \
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abort (); \
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return difference; \
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}
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MINUSCCZEXT
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