mirror of git://gcc.gnu.org/git/gcc.git
Add sparc vec_perm patterns when VIS2.
* config/sparc/sparc.md (vec_perm_constv8qi, vec_perm<mode>): New patterns. * config/sparc/sparc.c (sparc_expand_vec_perm_bmask): New function. * config/sparc/sparc-protos.h (sparc_expand_vec_perm_bmask): Declare. From-SVN: r180119
This commit is contained in:
Richard Henderson
David S. Miller
parent
d62fc6ed20
commit
9d4dedaa7b
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@ -53,6 +53,11 @@
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* config/sparc/sparc.md: Use register_or_zero_operand where rJ
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is the constraint.
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* config/sparc/sparc.md (vec_perm_constv8qi, vec_perm<mode>): New
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patterns.
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* config/sparc/sparc.c (sparc_expand_vec_perm_bmask): New function.
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* config/sparc/sparc-protos.h (sparc_expand_vec_perm_bmask): Declare.
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2011-10-17 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc-modes.def: Add single entry vector modes for
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@ -107,6 +107,7 @@ extern rtx gen_df_reg (rtx, int);
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extern void sparc_expand_compare_and_swap_12 (rtx, rtx, rtx, rtx);
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extern const char *output_v8plus_mult (rtx, rtx *, const char *);
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extern void sparc_expand_vector_init (rtx, rtx);
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extern void sparc_expand_vec_perm_bmask(enum machine_mode, rtx);
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#endif /* RTX_CODE */
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#endif /* __SPARC_PROTOS_H__ */
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@ -10863,6 +10863,113 @@ sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval)
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emit_move_insn (result, gen_lowpart (GET_MODE (result), res));
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}
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void
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sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel)
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{
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rtx t_1, t_2, t_3;
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sel = gen_lowpart (DImode, sel);
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switch (vmode)
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{
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case V2SImode:
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/* inp = xxxxxxxAxxxxxxxB */
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t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* t_1 = ....xxxxxxxAxxx. */
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sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
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GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT);
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t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
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GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT);
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/* sel = .......B */
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/* t_1 = ...A.... */
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sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
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/* sel = ...A...B */
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sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1);
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/* sel = AAAABBBB * 4 */
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t_1 = force_reg (SImode, GEN_INT (0x01230123));
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/* sel = { A*4, A*4+1, A*4+2, ... } */
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break;
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case V4HImode:
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/* inp = xxxAxxxBxxxCxxxD */
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t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
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NULL_RTX, 1, OPTAB_DIRECT);
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t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
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NULL_RTX, 1, OPTAB_DIRECT);
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t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* t_1 = ..xxxAxxxBxxxCxx */
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/* t_2 = ....xxxAxxxBxxxC */
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/* t_3 = ......xxxAxxxBxx */
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sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel),
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GEN_INT (0x07),
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NULL_RTX, 1, OPTAB_DIRECT);
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t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1),
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GEN_INT (0x0700),
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NULL_RTX, 1, OPTAB_DIRECT);
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t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2),
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GEN_INT (0x070000),
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NULL_RTX, 1, OPTAB_DIRECT);
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t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3),
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GEN_INT (0x07000000),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* sel = .......D */
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/* t_1 = .....C.. */
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/* t_2 = ...B.... */
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/* t_3 = .A...... */
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sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT);
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t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT);
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sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT);
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/* sel = .A.B.C.D */
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sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1);
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/* sel = AABBCCDD * 2 */
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t_1 = force_reg (SImode, GEN_INT (0x01010101));
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/* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
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break;
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case V8QImode:
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/* input = xAxBxCxDxExFxGxH */
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sel = expand_simple_binop (DImode, AND, sel,
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GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32
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| 0x0f0f0f0f),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* sel = .A.B.C.D.E.F.G.H */
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t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* t_1 = ..A.B.C.D.E.F.G. */
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sel = expand_simple_binop (DImode, IOR, sel, t_1,
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NULL_RTX, 1, OPTAB_DIRECT);
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/* sel = .AABBCCDDEEFFGGH */
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sel = expand_simple_binop (DImode, AND, sel,
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GEN_INT ((HOST_WIDE_INT)0xff00ff << 32
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| 0xff00ff),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* sel = ..AB..CD..EF..GH */
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t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* t_1 = ....AB..CD..EF.. */
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sel = expand_simple_binop (DImode, IOR, sel, t_1,
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NULL_RTX, 1, OPTAB_DIRECT);
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/* sel = ..ABABCDCDEFEFGH */
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sel = expand_simple_binop (DImode, AND, sel,
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GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* sel = ....ABCD....EFGH */
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t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16),
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NULL_RTX, 1, OPTAB_DIRECT);
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/* t_1 = ........ABCD.... */
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sel = gen_lowpart (SImode, sel);
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t_1 = gen_lowpart (SImode, t_1);
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break;
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default:
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gcc_unreachable ();
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}
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/* Always perform the final addition/merge within the bmask insn. */
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emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1));
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}
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/* Implement TARGET_FRAME_POINTER_REQUIRED. */
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static bool
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@ -8350,6 +8350,43 @@
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[(set_attr "type" "fga")
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(set_attr "fptype" "double")])
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;; The rtl expanders will happily convert constant permutations on other
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;; modes down to V8QI. Rely on this to avoid the complexity of the byte
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;; order of the permutation.
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(define_expand "vec_perm_constv8qi"
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[(match_operand:V8QI 0 "register_operand" "")
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(match_operand:V8QI 1 "register_operand" "")
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(match_operand:V8QI 2 "register_operand" "")
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(match_operand:V8QI 3 "" "")]
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"TARGET_VIS2"
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{
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unsigned int i, mask;
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rtx sel = operands[3];
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for (i = mask = 0; i < 8; ++i)
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mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4);
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sel = force_reg (SImode, gen_int_mode (mask, SImode));
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emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx));
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emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2]));
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DONE;
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})
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;; Unlike constant permutation, we can vastly simplify the compression of
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;; the 64-bit selector input to the 32-bit %gsr value by knowing what the
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;; width of the input is.
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(define_expand "vec_perm<mode>"
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[(match_operand:VM64 0 "register_operand" "")
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(match_operand:VM64 1 "register_operand" "")
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(match_operand:VM64 2 "register_operand" "")
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(match_operand:VM64 3 "register_operand" "")]
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"TARGET_VIS2"
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{
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sparc_expand_vec_perm_bmask (<MODE>mode, operands[3]);
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emit_insn (gen_bshuffle<mode>_vis (operands[0], operands[1], operands[2]));
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DONE;
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})
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;; VIS 2.0 adds edge variants which do not set the condition codes
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(define_insn "edge8n<P:mode>_vis"
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[(set (match_operand:P 0 "register_operand" "=r")
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