mirror of git://gcc.gnu.org/git/gcc.git
Move things around; Make unary operators work without hardware support.
2025-10-09 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/float16.md (vsx_xscvdpsp_sf): Move from vsx.md. (vsx_xscvdpspn_sf): Likewise. (neg<mode>2, FP16 iterator): Update code to not need specific 16-bit floating point hardware support; Add vector insns. (neg<mode>, VFP16 iterator): Likewise. (xor<mode>, FP16 iterator): Likewise. (xor<mode>, VFP16 iterator): Likewise. (abs<mode>2, FP16 iterator): Likewise. (abs<mode>2, VFP16 iterator): Likewise. (andc<mode>2, FP16 iterator): Likewise. (andc<mode>2, VFP16 iterator): Likewise. (nabs<mode>2, FP16 iterator): Likewise. (nabs<mode>2, VFP16 iterator): Likewise. (ior<mode>2, FP16 iterator): Likewise. (ior<mode>2, VFP16 iterator): Likewise. (vec_pack_trunc_v4sf_v8hf): New insn. (xvcvsphp_v8hf): Use vsx_register_operand instead of register_opernd. * config/rs6000/vsx.md (vsx_xscvdpsp_sf): Move to float16.md. (vsx_xscvdpspn_sf): Likewise.
This commit is contained in:
Michael Meissner
parent
73f4394670
commit
9e1c4fcb2e
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@ -193,6 +193,14 @@
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[(set_attr "type" "fpsimple")
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(set_attr "length" "12")])
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(define_insn "vsx_xscvdpsp_sf"
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[(set (match_operand:V4SF 0 "vsx_register_operand" "=f,?wa")
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(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f,wa")]
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UNSPEC_VSX_CVSPDP))]
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"VECTOR_UNIT_VSX_P (DFmode)"
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"xscvdpsp %x0,%x1"
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[(set_attr "type" "fp")])
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;; Vector shift left by 32 bits to get the 16-bit floating point value
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;; into the upper 32 bits for the conversion.
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(define_insn "<fp16_vector8>_shift_left_32bit"
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@ -235,6 +243,13 @@
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}
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[(set_attr "type" "fpsimple")])
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(define_insn "vsx_xscvdpspn_sf"
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[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
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(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVDPSPN))]
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"TARGET_XSCVDPSPN"
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"xscvdpspn %x0,%x1"
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[(set_attr "type" "fp")])
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;; Convert between HFmode/BFmode and 128-bit binary floating point and
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;; decimal floating point types. We use convert_move since some of the
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@ -666,151 +681,284 @@
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[(set_attr "type" "vecfloat")])
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;; Negate 16-bit floating point by XOR with -0.0. We only do this on
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;; power10, since we can easily load up -0.0 via XXSPLTIW.
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;; Negate 16-bit floating point by XOR with -0.0.
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(define_insn_and_split "neg<mode>2"
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[(set (match_operand:FP16_HW 0 "register_operand" "=wa,?wr")
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(neg:FP16_HW (match_operand:FP16_HW 1 "register_operand" "wa,wr")))
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(clobber (match_scratch:FP16_HW 2 "=&wa,&r"))]
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"TARGET_POWER10 && TARGET_PREFIXED"
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[(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr")
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(neg:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")))
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(clobber (match_scratch:FP16 2 "=&wa,&r"))]
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""
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"#"
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"&& 1"
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[(set (match_dup 2)
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(match_dup 3))
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(set (match_dup 0)
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(xor:FP16_HW (match_dup 1)
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(match_dup 2)))]
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(xor:FP16 (match_dup 1)
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(match_dup 2)))]
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{
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if (GET_CODE (operands[2]) == SCRATCH)
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operands[2] = gen_reg_rtx (<MODE>mode);
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REAL_VALUE_TYPE dconst;
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gcc_assert (real_from_string (&dconst, "-0.0") == 0);
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rtx rc = const_double_from_real_value (dconst, <MODE>mode);
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if (!TARGET_PREFIXED)
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rc = force_const_mem (<MODE>mode, rc);
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operands[3] = rc;
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}
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[(set_attr "type" "veclogical,integer")
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(set_attr "length" "16")])
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(define_insn_and_split "neg<mode>2"
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[(set (match_operand:VFP16 0 "vsx_register_operand" "=wa")
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(neg:VFP16 (match_operand:VFP16 1 "vsx_register_operand" "wa")))
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(clobber (match_scratch:VFP16 2 "=&wa"))]
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""
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"#"
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"&& 1"
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[(set (match_dup 2)
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(match_dup 3))
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(set (match_dup 0)
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(xor:VFP16 (match_dup 1)
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(match_dup 2)))]
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{
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if (GET_CODE (operands[2]) == SCRATCH)
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operands[2] = gen_reg_rtx (<MODE>mode);
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operands[3] = const_double_from_real_value (dconst, <MODE>mode);
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REAL_VALUE_TYPE dconst;
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gcc_assert (real_from_string (&dconst, "-0.0") == 0);
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rtx nz = const_double_from_real_value (dconst, <VEC_base>mode);
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rtvec v = gen_rtvec (8, nz, nz, nz, nz, nz, nz, nz, nz);
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rtx vrc = gen_rtx_CONST_VECTOR (<MODE>mode, v);
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if (!TARGET_PREFIXED)
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vrc = force_const_mem (<MODE>mode, vrc);
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operands[3] = vrc;
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}
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[(set_attr "type" "veclogical,integer")
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[(set_attr "type" "veclogical")
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(set_attr "length" "16")])
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;; XOR used to negate a 16-bit floating point type
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(define_insn "*xor<mode>3"
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[(set (match_operand:FP16_HW 0 "register_operand" "=wa,?wr")
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(xor:FP16_HW (match_operand:FP16_HW 1 "register_operand" "wa,wr")
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(match_operand:FP16_HW 2 "register_operand" "wa,wr")))]
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"TARGET_POWER10 && TARGET_PREFIXED"
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[(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr")
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(xor:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")
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(match_operand:FP16 2 "gpc_reg_operand" "wa,wr")))]
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""
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"@
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xxlxor %x0,%x1,%x2
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xor %0,%1,%2"
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[(set_attr "type" "veclogical,integer")])
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(define_insn "*xor<mode>3"
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[(set (match_operand:VFP16 0 "vsx_register_operand" "=wa")
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(xor:VFP16 (match_operand:VFP16 1 "vsx_register_operand" "wa")
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(match_operand:VFP16 2 "vsx_register_operand" "wa")))]
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""
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"xxlxor %x0,%x1,%x2"
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[(set_attr "type" "veclogical")])
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;; 16-bit floating point absolute value
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(define_insn_and_split "abs<mode>2"
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[(set (match_operand:FP16_HW 0 "register_operand" "=wa,?wr")
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(abs:FP16_HW
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(match_operand:FP16_HW 1 "register_operand" "wa,wr")))
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(clobber (match_scratch:FP16_HW 2 "=&wa,&r"))]
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"TARGET_POWER10 && TARGET_PREFIXED"
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[(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr")
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(abs:FP16
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(match_operand:FP16 1 "gpc_reg_operand" "wa,wr")))
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(clobber (match_scratch:FP16 2 "=&wa,&r"))]
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""
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"#"
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"&& 1"
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[(set (match_dup 2)
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(match_dup 3))
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(set (match_dup 0)
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(and:FP16_HW (match_dup 1)
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(not:FP16_HW (match_dup 2))))]
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(and:FP16 (match_dup 1)
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(not:FP16 (match_dup 2))))]
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{
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if (GET_CODE (operands[2]) == SCRATCH)
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operands[2] = gen_reg_rtx (<MODE>mode);
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REAL_VALUE_TYPE dconst;
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gcc_assert (real_from_string (&dconst, "-0.0") == 0);
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rtx rc = const_double_from_real_value (dconst, <MODE>mode);
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if (!TARGET_PREFIXED)
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rc = force_const_mem (<MODE>mode, rc);
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operands[3] = rc;
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}
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[(set_attr "type" "veclogical,integer")
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(set_attr "length" "16")])
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(define_insn_and_split "abs<mode>2"
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[(set (match_operand:VFP16 0 "vsx_register_operand" "=wa")
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(abs:VFP16
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(match_operand:VFP16 1 "vsx_register_operand" "wa")))
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(clobber (match_scratch:VFP16 2 "=&wa"))]
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""
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"#"
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"&& 1"
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[(set (match_dup 2)
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(match_dup 3))
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(set (match_dup 0)
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(and:VFP16 (match_dup 1)
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(not:VFP16 (match_dup 2))))]
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{
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if (GET_CODE (operands[2]) == SCRATCH)
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operands[2] = gen_reg_rtx (<MODE>mode);
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operands[3] = const_double_from_real_value (dconst, <MODE>mode);
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REAL_VALUE_TYPE dconst;
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gcc_assert (real_from_string (&dconst, "-0.0") == 0);
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rtx nz = const_double_from_real_value (dconst, <VEC_base>mode);
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rtvec v = gen_rtvec (8, nz, nz, nz, nz, nz, nz, nz, nz);
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rtx vrc = gen_rtx_CONST_VECTOR (<MODE>mode, v);
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if (!TARGET_PREFIXED)
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vrc = force_const_mem (<MODE>mode, vrc);
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operands[3] = vrc;
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}
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[(set_attr "type" "veclogical,integer")
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[(set_attr "type" "veclogical")
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(set_attr "length" "16")])
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;; ANDC used to clear the sign bit of a 16-bit floating point type
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;; for absolute value.
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(define_insn "*andc<mode>3"
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[(set (match_operand:FP16_HW 0 "register_operand" "=wa,?wr")
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(and:FP16_HW (match_operand:FP16_HW 1 "register_operand" "wa,wr")
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(not:FP16_HW
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(match_operand:FP16_HW 2 "register_operand" "wa,wr"))))]
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"TARGET_POWER10 && TARGET_PREFIXED"
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[(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr")
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(and:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")
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(not:FP16
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(match_operand:FP16 2 "gpc_reg_operand" "wa,wr"))))]
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""
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"@
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xxlandc %x0,%x1,%x2
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andc %0,%1,%2"
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[(set_attr "type" "veclogical,integer")])
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(define_insn "*andc<mode>3"
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[(set (match_operand:VFP16 0 "vsx_register_operand" "=wa")
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(and:VFP16 (match_operand:VFP16 1 "vsx_register_operand" "wa")
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(not:VFP16
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(match_operand:VFP16 2 "vsx_register_operand" "wa"))))]
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""
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"xxlandc %x0,%x1,%x2"
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[(set_attr "type" "veclogical")])
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;; 16-bit negative floating point absolute value
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(define_insn_and_split "*nabs<mode>2"
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[(set (match_operand:FP16_HW 0 "register_operand" "=wa,?wr")
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(neg:FP16_HW
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(abs:FP16_HW
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(match_operand:FP16_HW 1 "register_operand" "wa,wr"))))
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(clobber (match_scratch:FP16_HW 2 "=&wa,&r"))]
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"TARGET_POWER10 && TARGET_PREFIXED"
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[(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr")
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(neg:FP16
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(abs:FP16
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(match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))))
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(clobber (match_scratch:FP16 2 "=&wa,&r"))]
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""
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"#"
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"&& 1"
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[(set (match_dup 2)
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(match_dup 3))
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(set (match_dup 0)
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(ior:FP16_HW (match_dup 1)
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(match_dup 2)))]
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(ior:FP16 (match_dup 1)
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(match_dup 2)))]
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{
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REAL_VALUE_TYPE dconst;
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gcc_assert (real_from_string (&dconst, "-0.0") == 0);
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if (GET_CODE (operands[2]) == SCRATCH)
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operands[2] = gen_reg_rtx (<MODE>mode);
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operands[3] = const_double_from_real_value (dconst, <MODE>mode);
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REAL_VALUE_TYPE dconst;
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gcc_assert (real_from_string (&dconst, "-0.0") == 0);
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rtx rc = const_double_from_real_value (dconst, <MODE>mode);
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if (!TARGET_PREFIXED)
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rc = force_const_mem (<MODE>mode, rc);
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operands[3] = rc;
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}
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[(set_attr "type" "veclogical,integer")
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(set_attr "length" "16")])
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(define_insn_and_split "*nabs<mode>2"
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[(set (match_operand:VFP16 0 "vsx_register_operand" "=wa")
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(neg:VFP16
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(abs:VFP16
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(match_operand:VFP16 1 "vsx_register_operand" "wa"))))
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(clobber (match_scratch:VFP16 2 "=&wa"))]
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""
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"#"
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"&& 1"
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[(set (match_dup 2)
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(match_dup 3))
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(set (match_dup 0)
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(ior:VFP16 (match_dup 1)
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(match_dup 2)))]
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{
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if (GET_CODE (operands[2]) == SCRATCH)
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operands[2] = gen_reg_rtx (<MODE>mode);
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REAL_VALUE_TYPE dconst;
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gcc_assert (real_from_string (&dconst, "-0.0") == 0);
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rtx nz = const_double_from_real_value (dconst, <VEC_base>mode);
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rtvec v = gen_rtvec (8, nz, nz, nz, nz, nz, nz, nz, nz);
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rtx vrc = gen_rtx_CONST_VECTOR (<MODE>mode, v);
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if (!TARGET_PREFIXED)
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vrc = force_const_mem (<MODE>mode, vrc);
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operands[3] = vrc;
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}
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[(set_attr "type" "veclogical")
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(set_attr "length" "16")])
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;; OR used to set the sign bit of a 16-bit floating point type
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;; for negative absolute value.
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(define_insn "*ior<mode>3"
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[(set (match_operand:FP16_HW 0 "register_operand" "=wa,?wr")
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(ior:FP16_HW (match_operand:FP16_HW 1 "register_operand" "wa,wr")
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(match_operand:FP16_HW 2 "register_operand" "wa,wr")))]
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"TARGET_POWER10 && TARGET_PREFIXED"
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[(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr")
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(ior:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")
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(match_operand:FP16 2 "gpc_reg_operand" "wa,wr")))]
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""
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"@
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xxlor %x0,%x1,%x2
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or %0,%1,%2"
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[(set_attr "type" "veclogical,integer")])
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(define_insn "*ior<mode>3"
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[(set (match_operand:VFP16 0 "vsx_register_operand" "=wa")
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(ior:VFP16 (match_operand:VFP16 1 "vsx_register_operand" "wa")
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(match_operand:VFP16 2 "vsx_register_operand" "wa")))]
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""
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"xxlor %x0,%x1,%x2"
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[(set_attr "type" "veclogical")])
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;; Vector Pack support.
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;; Unfortunately the code assumes there is only one 16-bit floating
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;; point type. So we have to choose whether to support packing
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;; _Float16 or __bfloat16.
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;; Unfortunately the machine independent code assumes there is only one
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;; 16-bit floating point type. So we have to choose whether to support
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;; packing _Float16 or __bfloat16.
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;; (define_expand "vec_pack_trunc_v4sf"
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;; [(match_operand:V8HF 0 "vfloat_operand")
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;; (match_operand:V4SF 1 "vfloat_operand")
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;; (match_operand:V4SF 2 "vfloat_operand")]
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;; "TARGET_FLOAT16_HW"
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;; {
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;; rtx r1 = gen_reg_rtx (V8HFmode);
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;; rtx r2 = gen_reg_rtx (V8HFmode);
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;;
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;; emit_insn (gen_xvcvsphp_v8hf (r1, operands[1]));
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;; emit_insn (gen_xvcvsphp_v8hf (r2, operands[2]));
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;; rs6000_expand_extract_even (operands[0], r1, r2);
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;; DONE;
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;; })
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(define_expand "vec_pack_trunc_v4sf_v8hf"
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[(match_operand:V8HF 0 "vfloat_operand")
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(match_operand:V4SF 1 "vfloat_operand")
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(match_operand:V4SF 2 "vfloat_operand")]
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"TARGET_FLOAT16_HW"
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{
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rtx r1 = gen_reg_rtx (V8HFmode);
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rtx r2 = gen_reg_rtx (V8HFmode);
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emit_insn (gen_xvcvsphp_v8hf (r1, operands[1]));
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emit_insn (gen_xvcvsphp_v8hf (r2, operands[2]));
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rs6000_expand_extract_even (operands[0], r1, r2);
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DONE;
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})
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(define_expand "vec_pack_trunc_v4sf"
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[(match_operand:V8BF 0 "vfloat_operand")
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@ -827,43 +975,9 @@
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DONE;
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})
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;; (define_expand "vec_pack_trunc_v4sf"
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||||
;; [(match_operand 0 "vfloat_operand")
|
||||
;; (match_operand:V4SF 1 "vfloat_operand")
|
||||
;; (match_operand:V4SF 2 "vfloat_operand")]
|
||||
;; "TARGET_FLOAT16_HW || TARGET_BFLOAT16_HW"
|
||||
;; {
|
||||
;; machine_mode mode = GET_MODE (operands[0]);
|
||||
;; rtx r1, r2;
|
||||
;;
|
||||
;; if (mode == V8HFmode && TARGET_FLOAT16_HW)
|
||||
;; {
|
||||
;; r1 = gen_reg_rtx (V8HFmode);
|
||||
;; r2 = gen_reg_rtx (V8HFmode);
|
||||
;;
|
||||
;; emit_insn (gen_xvcvsphp_v8hf (r1, operands[1]));
|
||||
;; emit_insn (gen_xvcvsphp_v8hf (r2, operands[2]));
|
||||
;; }
|
||||
;;
|
||||
;; else if (mode == V8BFmode && TARGET_BFLOAT16_HW)
|
||||
;; {
|
||||
;; r1 = gen_reg_rtx (V8BFmode);
|
||||
;; r2 = gen_reg_rtx (V8BFmode);
|
||||
;;
|
||||
;; emit_insn (gen_xvcvspbf16_v8bf (r1, operands[1]));
|
||||
;; emit_insn (gen_xvcvspbf16_v8bf (r2, operands[2]));
|
||||
;; }
|
||||
;;
|
||||
;; else
|
||||
;; FAIL;
|
||||
;;
|
||||
;; rs6000_expand_extract_even (operands[0], r1, r2);
|
||||
;; DONE;
|
||||
;; })
|
||||
|
||||
;; Used for vector conversion to _Float16
|
||||
(define_insn "xvcvsphp_v8hf"
|
||||
[(set (match_operand:V8HF 0 "register_operand" "=wa")
|
||||
[(set (match_operand:V8HF 0 "vsx_register_operand" "=wa")
|
||||
(unspec:V8HF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
|
||||
UNSPEC_XVCVSPHP_V8HF))]
|
||||
"TARGET_P9_VECTOR"
|
||||
|
|
|
|||
|
|
@ -2388,14 +2388,6 @@
|
|||
"xscvdpsp %x0,%x1"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
(define_insn "vsx_xscvdpsp_sf"
|
||||
[(set (match_operand:V4SF 0 "vsx_register_operand" "=f,?wa")
|
||||
(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f,wa")]
|
||||
UNSPEC_VSX_CVSPDP))]
|
||||
"VECTOR_UNIT_VSX_P (DFmode)"
|
||||
"xscvdpsp %x0,%x1"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
(define_insn "vsx_xvcvspdp_be"
|
||||
[(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
|
||||
(float_extend:V2DF
|
||||
|
|
@ -2453,7 +2445,6 @@
|
|||
[(set_attr "type" "fp")])
|
||||
|
||||
;; Generate xvcvhpsp instruction
|
||||
;; Used for the built-in function
|
||||
(define_insn "vsx_xvcvhpsp"
|
||||
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
|
||||
(unspec:V4SF [(match_operand: V16QI 1 "vsx_register_operand" "wa")]
|
||||
|
|
@ -2463,7 +2454,6 @@
|
|||
[(set_attr "type" "vecfloat")])
|
||||
|
||||
;; Generate xvcvsphp
|
||||
;; Used for the built-in function
|
||||
(define_insn "vsx_xvcvsphp"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=wa")
|
||||
(unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
|
||||
|
|
@ -2491,14 +2481,6 @@
|
|||
"xscvdpspn %x0,%x1"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
(define_insn "vsx_xscvdpspn_sf"
|
||||
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
|
||||
(unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
|
||||
UNSPEC_VSX_CVDPSPN))]
|
||||
"TARGET_XSCVDPSPN"
|
||||
"xscvdpspn %x0,%x1"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
(define_insn "vsx_xscvspdpn"
|
||||
[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
|
||||
(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
|
||||
|
|
|
|||
Loading…
Reference in New Issue