mirror of git://gcc.gnu.org/git/gcc.git
aarch64-protos.h (aarch64_use_simple_return_insn_p): New prototype.
2018-12-17 Steve Ellcey <sellcey@cavium.com> * config/aarch64/aarch64-protos.h (aarch64_use_simple_return_insn_p): New prototype. (aarch64_epilogue_uses): Ditto. * config/aarch64/aarch64.c (aarch64_attribute_table): New array. (aarch64_simd_decl_p): New function. (aarch64_reg_save_mode): New function. (aarch64_function_ok_for_sibcall): Check for simd calls. (aarch64_layout_frame): Check for simd function. (aarch64_gen_storewb_pair): Handle E_TFmode. (aarch64_push_regs): Use aarch64_reg_save_mode to get mode. (aarch64_gen_loadwb_pair): Handle E_TFmode. (aarch64_pop_regs): Use aarch64_reg_save_mode to get mode. (aarch64_gen_store_pair): Handle E_TFmode. (aarch64_gen_load_pair): Ditto. (aarch64_save_callee_saves): Handle different mode sizes. (aarch64_restore_callee_saves): Ditto. (aarch64_components_for_bb): Check for simd function. (aarch64_epilogue_uses): New function. (aarch64_process_components): Check for simd function. (aarch64_expand_prologue): Ditto. (aarch64_expand_epilogue): Ditto. (aarch64_expand_call): Ditto. (aarch64_use_simple_return_insn_p): New function. (TARGET_ATTRIBUTE_TABLE): New define. * config/aarch64/aarch64.h (EPILOGUE_USES): Redefine. (FP_SIMD_SAVED_REGNUM_P): New macro. * config/aarch64/aarch64.md (simple_return): New define_expand. (load_pair_dw_tftf): New instruction. (store_pair_dw_tftf): Ditto. (loadwb_pair<TX:mode>_<P:mode>): Ditto. (storewb_pair<TX:mode>_<P:mode>): Ditto. From-SVN: r267208
This commit is contained in:
Steve Ellcey
Steve Ellcey
parent
4d814b6989
commit
a0d0b980f1
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@ -1,3 +1,37 @@
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2018-12-17 Steve Ellcey <sellcey@cavium.com>
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* config/aarch64/aarch64-protos.h (aarch64_use_simple_return_insn_p):
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New prototype.
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(aarch64_epilogue_uses): Ditto.
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* config/aarch64/aarch64.c (aarch64_attribute_table): New array.
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(aarch64_simd_decl_p): New function.
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(aarch64_reg_save_mode): New function.
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(aarch64_function_ok_for_sibcall): Check for simd calls.
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(aarch64_layout_frame): Check for simd function.
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(aarch64_gen_storewb_pair): Handle E_TFmode.
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(aarch64_push_regs): Use aarch64_reg_save_mode to get mode.
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(aarch64_gen_loadwb_pair): Handle E_TFmode.
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(aarch64_pop_regs): Use aarch64_reg_save_mode to get mode.
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(aarch64_gen_store_pair): Handle E_TFmode.
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(aarch64_gen_load_pair): Ditto.
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(aarch64_save_callee_saves): Handle different mode sizes.
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(aarch64_restore_callee_saves): Ditto.
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(aarch64_components_for_bb): Check for simd function.
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(aarch64_epilogue_uses): New function.
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(aarch64_process_components): Check for simd function.
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(aarch64_expand_prologue): Ditto.
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(aarch64_expand_epilogue): Ditto.
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(aarch64_expand_call): Ditto.
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(aarch64_use_simple_return_insn_p): New function.
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(TARGET_ATTRIBUTE_TABLE): New define.
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* config/aarch64/aarch64.h (EPILOGUE_USES): Redefine.
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(FP_SIMD_SAVED_REGNUM_P): New macro.
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* config/aarch64/aarch64.md (simple_return): New define_expand.
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(load_pair_dw_tftf): New instruction.
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(store_pair_dw_tftf): Ditto.
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(loadwb_pair<TX:mode>_<P:mode>): Ditto.
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(storewb_pair<TX:mode>_<P:mode>): Ditto.
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2018-12-17 Uros Bizjak <ubizjak@gmail.com>
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PR target/88502
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@ -471,6 +471,7 @@ bool aarch64_split_dimode_const_store (rtx, rtx);
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bool aarch64_symbolic_address_p (rtx);
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bool aarch64_uimm12_shift (HOST_WIDE_INT);
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bool aarch64_use_return_insn_p (void);
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bool aarch64_use_simple_return_insn_p (void);
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const char *aarch64_mangle_builtin_type (const_tree);
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const char *aarch64_output_casesi (rtx *);
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@ -556,6 +557,8 @@ void aarch64_split_simd_move (rtx, rtx);
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/* Check for a legitimate floating point constant for FMOV. */
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bool aarch64_float_const_representable_p (rtx);
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extern int aarch64_epilogue_uses (int);
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#if defined (RTX_CODE)
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void aarch64_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
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rtx label_ref);
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@ -1141,6 +1141,15 @@ static const struct processor *selected_tune;
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/* The current tuning set. */
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struct tune_params aarch64_tune_params = generic_tunings;
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/* Table of machine attributes. */
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static const struct attribute_spec aarch64_attribute_table[] =
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{
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/* { name, min_len, max_len, decl_req, type_req, fn_type_req,
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affects_type_identity, handler, exclude } */
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{ "aarch64_vector_pcs", 0, 0, false, true, true, false, NULL, NULL },
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{ NULL, 0, 0, false, false, false, false, NULL, NULL }
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};
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#define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
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/* An ISA extension in the co-processor and main instruction set space. */
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@ -1523,6 +1532,39 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
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return false;
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}
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/* Return true if this is a definition of a vectorized simd function. */
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static bool
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aarch64_simd_decl_p (tree fndecl)
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{
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tree fntype;
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if (fndecl == NULL)
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return false;
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fntype = TREE_TYPE (fndecl);
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if (fntype == NULL)
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return false;
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/* Functions with the aarch64_vector_pcs attribute use the simd ABI. */
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if (lookup_attribute ("aarch64_vector_pcs", TYPE_ATTRIBUTES (fntype)) != NULL)
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return true;
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return false;
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}
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/* Return the mode a register save/restore should use. DImode for integer
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registers, DFmode for FP registers in non-SIMD functions (they only save
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the bottom half of a 128 bit register), or TFmode for FP registers in
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SIMD functions. */
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static machine_mode
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aarch64_reg_save_mode (tree fndecl, unsigned regno)
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{
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return GP_REGNUM_P (regno)
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? E_DImode
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: (aarch64_simd_decl_p (fndecl) ? E_TFmode : E_DFmode);
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}
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/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
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the lower 64 bits of a 128-bit register. Tell the compiler the callee
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clobbers the top 64 bits when restoring the bottom 64 bits. */
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@ -3349,7 +3391,9 @@ static bool
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aarch64_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
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tree exp ATTRIBUTE_UNUSED)
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{
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/* Currently, always true. */
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if (aarch64_simd_decl_p (cfun->decl) != aarch64_simd_decl_p (decl))
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return false;
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return true;
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}
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@ -4210,6 +4254,7 @@ aarch64_layout_frame (void)
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{
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HOST_WIDE_INT offset = 0;
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int regno, last_fp_reg = INVALID_REGNUM;
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bool simd_function = aarch64_simd_decl_p (cfun->decl);
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cfun->machine->frame.emit_frame_chain = aarch64_needs_frame_chain ();
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@ -4223,6 +4268,17 @@ aarch64_layout_frame (void)
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cfun->machine->frame.wb_candidate1 = INVALID_REGNUM;
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cfun->machine->frame.wb_candidate2 = INVALID_REGNUM;
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/* If this is a non-leaf simd function with calls we assume that
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at least one of those calls is to a non-simd function and thus
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we must save V8 to V23 in the prologue. */
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if (simd_function && !crtl->is_leaf)
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{
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for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
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if (FP_SIMD_SAVED_REGNUM_P (regno))
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df_set_regs_ever_live (regno, true);
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}
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/* First mark all the registers that really need to be saved... */
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for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++)
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cfun->machine->frame.reg_offset[regno] = SLOT_NOT_REQUIRED;
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@ -4245,7 +4301,8 @@ aarch64_layout_frame (void)
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for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
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if (df_regs_ever_live_p (regno)
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&& !call_used_regs[regno])
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&& (!call_used_regs[regno]
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|| (simd_function && FP_SIMD_SAVED_REGNUM_P (regno))))
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{
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cfun->machine->frame.reg_offset[regno] = SLOT_REQUIRED;
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last_fp_reg = regno;
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@ -4287,7 +4344,10 @@ aarch64_layout_frame (void)
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{
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/* If there is an alignment gap between integer and fp callee-saves,
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allocate the last fp register to it if possible. */
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if (regno == last_fp_reg && has_align_gap && (offset & 8) == 0)
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if (regno == last_fp_reg
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&& has_align_gap
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&& !simd_function
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&& (offset & 8) == 0)
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{
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cfun->machine->frame.reg_offset[regno] = max_int_offset;
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break;
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@ -4299,7 +4359,7 @@ aarch64_layout_frame (void)
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else if (cfun->machine->frame.wb_candidate2 == INVALID_REGNUM
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&& cfun->machine->frame.wb_candidate1 >= V0_REGNUM)
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cfun->machine->frame.wb_candidate2 = regno;
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offset += UNITS_PER_WORD;
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offset += simd_function ? UNITS_PER_VREG : UNITS_PER_WORD;
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}
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offset = ROUND_UP (offset, STACK_BOUNDARY / BITS_PER_UNIT);
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@ -4442,6 +4502,10 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
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return gen_storewb_pairdf_di (base, base, reg, reg2,
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GEN_INT (-adjustment),
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GEN_INT (UNITS_PER_WORD - adjustment));
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case E_TFmode:
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return gen_storewb_pairtf_di (base, base, reg, reg2,
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GEN_INT (-adjustment),
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GEN_INT (UNITS_PER_VREG - adjustment));
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default:
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gcc_unreachable ();
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}
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@ -4454,7 +4518,7 @@ static void
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aarch64_push_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment)
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{
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rtx_insn *insn;
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machine_mode mode = (regno1 <= R30_REGNUM) ? E_DImode : E_DFmode;
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machine_mode mode = aarch64_reg_save_mode (cfun->decl, regno1);
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if (regno2 == INVALID_REGNUM)
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return aarch64_pushwb_single_reg (mode, regno1, adjustment);
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@ -4484,6 +4548,9 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
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case E_DFmode:
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return gen_loadwb_pairdf_di (base, base, reg, reg2, GEN_INT (adjustment),
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GEN_INT (UNITS_PER_WORD));
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case E_TFmode:
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return gen_loadwb_pairtf_di (base, base, reg, reg2, GEN_INT (adjustment),
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GEN_INT (UNITS_PER_VREG));
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default:
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gcc_unreachable ();
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}
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@ -4497,7 +4564,7 @@ static void
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aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment,
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rtx *cfi_ops)
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{
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machine_mode mode = (regno1 <= R30_REGNUM) ? E_DImode : E_DFmode;
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machine_mode mode = aarch64_reg_save_mode (cfun->decl, regno1);
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rtx reg1 = gen_rtx_REG (mode, regno1);
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*cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg1, *cfi_ops);
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@ -4532,6 +4599,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
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case E_DFmode:
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return gen_store_pair_dw_dfdf (mem1, reg1, mem2, reg2);
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case E_TFmode:
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return gen_store_pair_dw_tftf (mem1, reg1, mem2, reg2);
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default:
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gcc_unreachable ();
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}
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@ -4552,6 +4622,9 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
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case E_DFmode:
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return gen_load_pair_dw_dfdf (reg1, mem1, reg2, mem2);
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case E_TFmode:
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return gen_load_pair_dw_tftf (reg1, mem1, reg2, mem2);
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default:
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gcc_unreachable ();
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}
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@ -4591,6 +4664,7 @@ aarch64_save_callee_saves (machine_mode mode, poly_int64 start_offset,
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{
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rtx reg, mem;
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poly_int64 offset;
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int offset_diff;
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if (skip_wb
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&& (regno == cfun->machine->frame.wb_candidate1
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@ -4606,12 +4680,12 @@ aarch64_save_callee_saves (machine_mode mode, poly_int64 start_offset,
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offset));
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regno2 = aarch64_next_callee_save (regno + 1, limit);
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offset_diff = cfun->machine->frame.reg_offset[regno2]
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- cfun->machine->frame.reg_offset[regno];
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if (regno2 <= limit
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&& !cfun->machine->reg_is_wrapped_separately[regno2]
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&& ((cfun->machine->frame.reg_offset[regno] + UNITS_PER_WORD)
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== cfun->machine->frame.reg_offset[regno2]))
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&& known_eq (GET_MODE_SIZE (mode), offset_diff))
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{
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rtx reg2 = gen_rtx_REG (mode, regno2);
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rtx mem2;
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@ -4659,6 +4733,7 @@ aarch64_restore_callee_saves (machine_mode mode,
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continue;
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rtx reg, mem;
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int offset_diff;
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if (skip_wb
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&& (regno == cfun->machine->frame.wb_candidate1
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@ -4670,11 +4745,12 @@ aarch64_restore_callee_saves (machine_mode mode,
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mem = gen_frame_mem (mode, plus_constant (Pmode, base_rtx, offset));
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regno2 = aarch64_next_callee_save (regno + 1, limit);
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offset_diff = cfun->machine->frame.reg_offset[regno2]
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- cfun->machine->frame.reg_offset[regno];
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if (regno2 <= limit
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&& !cfun->machine->reg_is_wrapped_separately[regno2]
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&& ((cfun->machine->frame.reg_offset[regno] + UNITS_PER_WORD)
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== cfun->machine->frame.reg_offset[regno2]))
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&& known_eq (GET_MODE_SIZE (mode), offset_diff))
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{
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rtx reg2 = gen_rtx_REG (mode, regno2);
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rtx mem2;
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@ -4808,13 +4884,15 @@ aarch64_components_for_bb (basic_block bb)
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bitmap in = DF_LIVE_IN (bb);
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bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
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bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
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bool simd_function = aarch64_simd_decl_p (cfun->decl);
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sbitmap components = sbitmap_alloc (LAST_SAVED_REGNUM + 1);
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bitmap_clear (components);
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/* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
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for (unsigned regno = 0; regno <= LAST_SAVED_REGNUM; regno++)
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if ((!call_used_regs[regno])
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if ((!call_used_regs[regno]
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|| (simd_function && FP_SIMD_SAVED_REGNUM_P (regno)))
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&& (bitmap_bit_p (in, regno)
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|| bitmap_bit_p (gen, regno)
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|| bitmap_bit_p (kill, regno)))
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@ -4885,9 +4963,11 @@ aarch64_process_components (sbitmap components, bool prologue_p)
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while (regno != last_regno)
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{
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/* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
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so DFmode for the vector registers is enough. */
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machine_mode mode = GP_REGNUM_P (regno) ? E_DImode : E_DFmode;
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/* AAPCS64 section 5.1.2 requires only the low 64 bits to be saved
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so DFmode for the vector registers is enough. For simd functions
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we want to save the low 128 bits. */
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machine_mode mode = aarch64_reg_save_mode (cfun->decl, regno);
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rtx reg = gen_rtx_REG (mode, regno);
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poly_int64 offset = cfun->machine->frame.reg_offset[regno];
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if (!frame_pointer_needed)
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@ -4916,6 +4996,7 @@ aarch64_process_components (sbitmap components, bool prologue_p)
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mergeable with the current one into a pair. */
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if (!satisfies_constraint_Ump (mem)
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|| GP_REGNUM_P (regno) != GP_REGNUM_P (regno2)
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|| (aarch64_simd_decl_p (cfun->decl) && FP_REGNUM_P (regno))
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|| maybe_ne ((offset2 - cfun->machine->frame.reg_offset[regno]),
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GET_MODE_SIZE (mode)))
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{
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@ -5231,6 +5312,28 @@ aarch64_allocate_and_probe_stack_space (rtx temp1, rtx temp2,
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}
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}
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/* Return 1 if the register is used by the epilogue. We need to say the
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return register is used, but only after epilogue generation is complete.
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Note that in the case of sibcalls, the values "used by the epilogue" are
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considered live at the start of the called function.
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For SIMD functions we need to return 1 for FP registers that are saved and
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restored by a function but are not zero in call_used_regs. If we do not do
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this optimizations may remove the restore of the register. */
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int
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aarch64_epilogue_uses (int regno)
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{
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if (epilogue_completed)
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{
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if (regno == LR_REGNUM)
|
||||
return 1;
|
||||
if (aarch64_simd_decl_p (cfun->decl) && FP_SIMD_SAVED_REGNUM_P (regno))
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
|
||||
is saved at BASE + OFFSET. */
|
||||
|
||||
|
|
@ -5405,6 +5508,10 @@ aarch64_expand_prologue (void)
|
|||
|
||||
aarch64_save_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
|
||||
callee_adjust != 0 || emit_frame_chain);
|
||||
if (aarch64_simd_decl_p (cfun->decl))
|
||||
aarch64_save_callee_saves (TFmode, callee_offset, V0_REGNUM, V31_REGNUM,
|
||||
callee_adjust != 0 || emit_frame_chain);
|
||||
else
|
||||
aarch64_save_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
|
||||
callee_adjust != 0 || emit_frame_chain);
|
||||
|
||||
|
|
@ -5432,6 +5539,19 @@ aarch64_use_return_insn_p (void)
|
|||
return known_eq (cfun->machine->frame.frame_size, 0);
|
||||
}
|
||||
|
||||
/* Return false for non-leaf SIMD functions in order to avoid
|
||||
shrink-wrapping them. Doing this will lose the necessary
|
||||
save/restore of FP registers. */
|
||||
|
||||
bool
|
||||
aarch64_use_simple_return_insn_p (void)
|
||||
{
|
||||
if (aarch64_simd_decl_p (cfun->decl) && !crtl->is_leaf)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Generate the epilogue instructions for returning from a function.
|
||||
This is almost exactly the reverse of the prolog sequence, except
|
||||
that we need to insert barriers to avoid scheduling loads that read
|
||||
|
|
@ -5500,6 +5620,10 @@ aarch64_expand_epilogue (bool for_sibcall)
|
|||
|
||||
aarch64_restore_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
|
||||
callee_adjust != 0, &cfi_ops);
|
||||
if (aarch64_simd_decl_p (cfun->decl))
|
||||
aarch64_restore_callee_saves (TFmode, callee_offset, V0_REGNUM, V31_REGNUM,
|
||||
callee_adjust != 0, &cfi_ops);
|
||||
else
|
||||
aarch64_restore_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
|
||||
callee_adjust != 0, &cfi_ops);
|
||||
|
||||
|
|
@ -18422,6 +18546,9 @@ aarch64_libgcc_floating_mode_supported_p
|
|||
#undef TARGET_ESTIMATED_POLY_VALUE
|
||||
#define TARGET_ESTIMATED_POLY_VALUE aarch64_estimated_poly_value
|
||||
|
||||
#undef TARGET_ATTRIBUTE_TABLE
|
||||
#define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table
|
||||
|
||||
#if CHECKING_P
|
||||
#undef TARGET_RUN_TARGET_SELFTESTS
|
||||
#define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests
|
||||
|
|
|
|||
|
|
@ -409,13 +409,7 @@ extern unsigned aarch64_architecture_version;
|
|||
V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \
|
||||
}
|
||||
|
||||
/* Say that the return address register is used by the epilogue, but only after
|
||||
epilogue generation is complete. Note that in the case of sibcalls, the
|
||||
values "used by the epilogue" are considered live at the start of the called
|
||||
function. */
|
||||
|
||||
#define EPILOGUE_USES(REGNO) \
|
||||
(epilogue_completed && (REGNO) == LR_REGNUM)
|
||||
#define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO))
|
||||
|
||||
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
||||
the stack pointer does not matter. This is only true if the function
|
||||
|
|
@ -523,6 +517,8 @@ extern unsigned aarch64_architecture_version;
|
|||
#define PR_LO_REGNUM_P(REGNO)\
|
||||
(((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM))
|
||||
|
||||
#define FP_SIMD_SAVED_REGNUM_P(REGNO) \
|
||||
(((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM))
|
||||
|
||||
/* Register and constant classes. */
|
||||
|
||||
|
|
|
|||
|
|
@ -727,7 +727,7 @@
|
|||
|
||||
(define_insn "simple_return"
|
||||
[(simple_return)]
|
||||
""
|
||||
"aarch64_use_simple_return_insn_p ()"
|
||||
"ret"
|
||||
[(set_attr "type" "branch")]
|
||||
)
|
||||
|
|
@ -1387,6 +1387,21 @@
|
|||
(set_attr "arch" "*,fp")]
|
||||
)
|
||||
|
||||
(define_insn "load_pair_dw_tftf"
|
||||
[(set (match_operand:TF 0 "register_operand" "=w")
|
||||
(match_operand:TF 1 "aarch64_mem_pair_operand" "Ump"))
|
||||
(set (match_operand:TF 2 "register_operand" "=w")
|
||||
(match_operand:TF 3 "memory_operand" "m"))]
|
||||
"TARGET_SIMD
|
||||
&& rtx_equal_p (XEXP (operands[3], 0),
|
||||
plus_constant (Pmode,
|
||||
XEXP (operands[1], 0),
|
||||
GET_MODE_SIZE (TFmode)))"
|
||||
"ldp\\t%q0, %q2, %1"
|
||||
[(set_attr "type" "neon_ldp_q")
|
||||
(set_attr "fp" "yes")]
|
||||
)
|
||||
|
||||
;; Operands 0 and 2 are tied together by the final condition; so we allow
|
||||
;; fairly lax checking on the second memory operation.
|
||||
(define_insn "store_pair_sw_<SX:mode><SX2:mode>"
|
||||
|
|
@ -1422,6 +1437,21 @@
|
|||
(set_attr "arch" "*,fp")]
|
||||
)
|
||||
|
||||
(define_insn "store_pair_dw_tftf"
|
||||
[(set (match_operand:TF 0 "aarch64_mem_pair_operand" "=Ump")
|
||||
(match_operand:TF 1 "register_operand" "w"))
|
||||
(set (match_operand:TF 2 "memory_operand" "=m")
|
||||
(match_operand:TF 3 "register_operand" "w"))]
|
||||
"TARGET_SIMD &&
|
||||
rtx_equal_p (XEXP (operands[2], 0),
|
||||
plus_constant (Pmode,
|
||||
XEXP (operands[0], 0),
|
||||
GET_MODE_SIZE (TFmode)))"
|
||||
"stp\\t%q1, %q3, %0"
|
||||
[(set_attr "type" "neon_stp_q")
|
||||
(set_attr "fp" "yes")]
|
||||
)
|
||||
|
||||
;; Load pair with post-index writeback. This is primarily used in function
|
||||
;; epilogues.
|
||||
(define_insn "loadwb_pair<GPI:mode>_<P:mode>"
|
||||
|
|
@ -1454,6 +1484,21 @@
|
|||
[(set_attr "type" "neon_load1_2reg")]
|
||||
)
|
||||
|
||||
(define_insn "loadwb_pair<TX:mode>_<P:mode>"
|
||||
[(parallel
|
||||
[(set (match_operand:P 0 "register_operand" "=k")
|
||||
(plus:P (match_operand:P 1 "register_operand" "0")
|
||||
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
|
||||
(set (match_operand:TX 2 "register_operand" "=w")
|
||||
(mem:TX (match_dup 1)))
|
||||
(set (match_operand:TX 3 "register_operand" "=w")
|
||||
(mem:TX (plus:P (match_dup 1)
|
||||
(match_operand:P 5 "const_int_operand" "n"))))])]
|
||||
"TARGET_SIMD && INTVAL (operands[5]) == GET_MODE_SIZE (<TX:MODE>mode)"
|
||||
"ldp\\t%q2, %q3, [%1], %4"
|
||||
[(set_attr "type" "neon_ldp_q")]
|
||||
)
|
||||
|
||||
;; Store pair with pre-index writeback. This is primarily used in function
|
||||
;; prologues.
|
||||
(define_insn "storewb_pair<GPI:mode>_<P:mode>"
|
||||
|
|
@ -1488,6 +1533,24 @@
|
|||
[(set_attr "type" "neon_store1_2reg<q>")]
|
||||
)
|
||||
|
||||
(define_insn "storewb_pair<TX:mode>_<P:mode>"
|
||||
[(parallel
|
||||
[(set (match_operand:P 0 "register_operand" "=&k")
|
||||
(plus:P (match_operand:P 1 "register_operand" "0")
|
||||
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
|
||||
(set (mem:TX (plus:P (match_dup 0)
|
||||
(match_dup 4)))
|
||||
(match_operand:TX 2 "register_operand" "w"))
|
||||
(set (mem:TX (plus:P (match_dup 0)
|
||||
(match_operand:P 5 "const_int_operand" "n")))
|
||||
(match_operand:TX 3 "register_operand" "w"))])]
|
||||
"TARGET_SIMD
|
||||
&& INTVAL (operands[5])
|
||||
== INTVAL (operands[4]) + GET_MODE_SIZE (<TX:MODE>mode)"
|
||||
"stp\\t%q2, %q3, [%0, %4]!"
|
||||
[(set_attr "type" "neon_stp_q")]
|
||||
)
|
||||
|
||||
;; -------------------------------------------------------------------
|
||||
;; Sign/Zero extension
|
||||
;; -------------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Reference in New Issue