rs6000.c: Add handling for early expansion of vector multiply builtins.

2016-12-19  Will Schmidt  <will_schmidt@vnet.ibm.com>

        *  config/rs6000/rs6000.c: Add handling for early expansion of
        vector multiply builtins.
    
[gcc/testsuite]

2016-12-19  Will Schmidt  <will_schmidt@vnet.ibm.com>

        *  gcc.dg/vmx/mult-even-odd-be-order.c : Mark
        variables as volatile.
        *  gcc.target/powerpc/fold-vec-mult-char.c : New.
        *  gcc.target/powerpc/fold-vec-mult-float.c : New.
        *  gcc.target/powerpc/fold-vec-mult-floatdouble.c : New.
        *  gcc.target/powerpc/fold-vec-mult-int.c : New.
        *  gcc.target/powerpc/fold-vec-mult-int128-p8.c : New.
        *  gcc.target/powerpc/fold-vec-mult-int128-p9.c : New.
        *  gcc.target/powerpc/fold-vec-mult-longlong.c : New.
        *  gcc.target/powerpc/fold-vec-mult-short.c : New.

From-SVN: r243807

ChangeLog

@@ -1,3 +1,8 @@
+2016-12-19  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	*  config/rs6000/rs6000.c: Add handling for early expansion of
+	vector multiply builtins.
+
 2016-12-19  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for

gcc/config/rs6000/rs6000.c

@@ -16581,6 +16581,36 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
 	gsi_replace (gsi, g, true);
 	return true;
       }
+    /* Even element flavors of vec_mul (signed). */
+    case ALTIVEC_BUILTIN_VMULESB:
+    case ALTIVEC_BUILTIN_VMULESH:
+    /* Even element flavors of vec_mul (unsigned).  */
+    case ALTIVEC_BUILTIN_VMULEUB:
+    case ALTIVEC_BUILTIN_VMULEUH:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
+    /* Odd element flavors of vec_mul (signed).  */
+    case ALTIVEC_BUILTIN_VMULOSB:
+    case ALTIVEC_BUILTIN_VMULOSH:
+    /* Odd element flavors of vec_mul (unsigned). */
+    case ALTIVEC_BUILTIN_VMULOUB:
+    case ALTIVEC_BUILTIN_VMULOUH:
+      {
+	arg0 = gimple_call_arg (stmt, 0);
+	arg1 = gimple_call_arg (stmt, 1);
+	lhs = gimple_call_lhs (stmt);
+	gimple *g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
+	gimple_set_location (g, gimple_location (stmt));
+	gsi_replace (gsi, g, true);
+	return true;
+      }
 
     default:
       break;

gcc/testsuite/ChangeLog

@@ -1,3 +1,16 @@
+2016-12-19  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	*  gcc.dg/vmx/mult-even-odd-be-order.c: Mark
+	variables as volatile.
+	*  gcc.target/powerpc/fold-vec-mult-char.c: New.
+	*  gcc.target/powerpc/fold-vec-mult-float.c: New.
+	*  gcc.target/powerpc/fold-vec-mult-floatdouble.c: New.
+	*  gcc.target/powerpc/fold-vec-mult-int.c: New.
+	*  gcc.target/powerpc/fold-vec-mult-int128-p8.c: New.
+	*  gcc.target/powerpc/fold-vec-mult-int128-p9.c: New.
+	*  gcc.target/powerpc/fold-vec-mult-longlong.c: New.
+	*  gcc.target/powerpc/fold-vec-mult-short.c: New.
+
 2016-12-19  Will Schmidt  <will_schmidt@vnet.ibm.com>
  
 	* gcc.target/powerpc/fold-vec-sub-char.c: New.

gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c

@@ -4,18 +4,18 @@
 
 static void test()
 {
-  vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
-  vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};
-  vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
-  vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};
-  vector unsigned short vusa = {0,1,2,3,4,5,6,7};
-  vector unsigned short vusb = {2,3,2,3,2,3,2,3};
-  vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};
-  vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};
-  vector unsigned short vuse, vuso;
-  vector signed short vsse, vsso;
-  vector unsigned int vuie, vuio;
-  vector signed int vsie, vsio;
+  volatile vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+  volatile vector unsigned char vucb = {2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3};
+  volatile vector signed char vsca = {-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7};
+  volatile vector signed char vscb = {2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3,2,-3};
+  volatile vector unsigned short vusa = {0,1,2,3,4,5,6,7};
+  volatile vector unsigned short vusb = {2,3,2,3,2,3,2,3};
+  volatile vector signed short vssa = {-4,-3,-2,-1,0,1,2,3};
+  volatile vector signed short vssb = {2,-3,2,-3,2,-3,2,-3};
+  volatile vector unsigned short vuse, vuso;
+  volatile vector signed short vsse, vsso;
+  volatile vector unsigned int vuie, vuio;
+  volatile vector signed int vsie, vsio;
 
   vuse = vec_mule (vuca, vucb);
   vuso = vec_mulo (vuca, vucb);

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-char.c

@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with char
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed char
+test3 (vector signed char x, vector signed char y)
+{
+  return vec_mul (x, y);
+}
+
+vector unsigned char
+test6 (vector unsigned char x, vector unsigned char y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]vmulesb" 2 } } */
+/* { dg-final { scan-assembler-times "\[ \t\]vmulosb" 2 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-float.c

@@ -0,0 +1,17 @@
+/* Verify that overloaded built-ins for vec_mul with float
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mvsx" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]xvmulsp" 1 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-floatdouble.c

@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with float and
+   double inputs for VSX produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec -mvsx" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+  return vec_mul (x, y);
+}
+
+vector double
+test2 (vector double x, vector double y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]xvmulsp" 1 } } */
+/* { dg-final { scan-assembler-times "\[ \t\]xvmuldp" 1 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c

@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with int
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed int
+test3 (vector signed int x, vector signed int y)
+{
+  return vec_mul (x, y);
+}
+
+vector unsigned int
+test6 (vector unsigned int x, vector unsigned int y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]vmuluwm" 2 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c

@@ -0,0 +1,25 @@
+/* Verify that overloaded built-ins for vec_mul with __int128
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
+
+#include "altivec.h"
+
+vector signed __int128
+test1 (vector signed __int128 x, vector signed __int128 y)
+{
+  return vec_mul (x, y);
+}
+
+vector unsigned __int128
+test2 (vector unsigned __int128 x, vector unsigned __int128 y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]mulld " 6 } } */
+/* { dg-final { scan-assembler-times "\[ \t\]mulhdu" 2 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c

@@ -0,0 +1,25 @@
+/* Verify that overloaded built-ins for vec_mul with __int128
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_float128_hw_ok } */
+/* { dg-require-effective-target int128 } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-maltivec -mvsx -mcpu=power9 -O2" } */
+/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
+
+#include "altivec.h"
+
+vector signed __int128
+test1 (vector signed __int128 x, vector signed __int128 y)
+{
+  return vec_mul (x, y);
+}
+
+vector unsigned __int128
+test2 (vector unsigned __int128 x, vector unsigned __int128 y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]xsmulqp" 2 } } */

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c

@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x, vector signed long long y)
+{
+  return vec_mul (x, y);
+}
+
+vector unsigned long long
+test6 (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 } } */
+

gcc/testsuite/gcc.target/powerpc/fold-vec-mult-short.c

@@ -0,0 +1,23 @@
+/* Verify that overloaded built-ins for vec_mul with short
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed short
+test3 (vector signed short x, vector signed short y)
+{
+  return vec_mul (x, y);
+}
+
+vector unsigned short
+test6 (vector unsigned short x, vector unsigned short y)
+{
+  return vec_mul (x, y);
+}
+
+/* { dg-final { scan-assembler-times "\[ \t\]vmladduhm" 2 } } */
+