diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 930c46815732..db2048072afe 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,124 @@ +2015-05-21 Sandra Loosemore + + * gcc.target/arm/simd/simd.exp: Skip all tests if no arm_neon_ok + effective target support. If no arm_neon_hw support, do not attempt + to execute the tests; only compile them. + * gcc.target/arm/simd/vextf32_1.c: Remove explicit "dg-do run" + and "dg-require-effective-target arm_neon_ok". + * gcc.target/arm/simd/vextp16_1.c: Likewise. + * gcc.target/arm/simd/vextp64_1.c: Likewise. + * gcc.target/arm/simd/vextp8_1.c: Likewise. + * gcc.target/arm/simd/vextQf32_1.c: Likewise. + * gcc.target/arm/simd/vextQp16_1.c: Likewise. + * gcc.target/arm/simd/vextQp64_1.c: Likewise. + * gcc.target/arm/simd/vextQp8_1.c: Likewise. + * gcc.target/arm/simd/vextQs16_1.c: Likewise. + * gcc.target/arm/simd/vextQs32_1.c: Likewise. + * gcc.target/arm/simd/vextQs64_1.c: Likewise. + * gcc.target/arm/simd/vextQs8_1.c: Likewise. + * gcc.target/arm/simd/vextQu16_1.c: Likewise. + * gcc.target/arm/simd/vextQu32_1.c: Likewise. + * gcc.target/arm/simd/vextQu64_1.c: Likewise. + * gcc.target/arm/simd/vextQu8_1.c: Likewise. + * gcc.target/arm/simd/vexts16_1.c: Likewise. + * gcc.target/arm/simd/vexts32_1.c: Likewise. + * gcc.target/arm/simd/vexts64_1.c: Likewise. + * gcc.target/arm/simd/vexts8_1.c: Likewise. + * gcc.target/arm/simd/vextu16_1.c: Likewise. + * gcc.target/arm/simd/vextu32_1.c: Likewise. + * gcc.target/arm/simd/vextu64_1.c: Likewise. + * gcc.target/arm/simd/vextu8_1.c: Likewise. + * gcc.target/arm/simd/vrev16p8_1.c: Likewise. + * gcc.target/arm/simd/vrev16qp8_1.c: Likewise. + * gcc.target/arm/simd/vrev16qs8_1.c: Likewise. + * gcc.target/arm/simd/vrev16qu8_1.c: Likewise. + * gcc.target/arm/simd/vrev16s8_1.c: Likewise. + * gcc.target/arm/simd/vrev16u8_1.c: Likewise. + * gcc.target/arm/simd/vrev32p16_1.c: Likewise. + * gcc.target/arm/simd/vrev32p8_1.c: Likewise. + * gcc.target/arm/simd/vrev32qp16_1.c: Likewise. + * gcc.target/arm/simd/vrev32qp8_1.c: Likewise. + * gcc.target/arm/simd/vrev32qs16_1.c: Likewise. + * gcc.target/arm/simd/vrev32qs8_1.c: Likewise. + * gcc.target/arm/simd/vrev32qu16_1.c: Likewise. + * gcc.target/arm/simd/vrev32qu8_1.c: Likewise. + * gcc.target/arm/simd/vrev32s16_1.c: Likewise. + * gcc.target/arm/simd/vrev32s8_1.c: Likewise. + * gcc.target/arm/simd/vrev32u16_1.c: Likewise. + * gcc.target/arm/simd/vrev32u8_1.c: Likewise. + * gcc.target/arm/simd/vrev64f32_1.c: Likewise. + * gcc.target/arm/simd/vrev64p16_1.c: Likewise. + * gcc.target/arm/simd/vrev64p8_1.c: Likewise. + * gcc.target/arm/simd/vrev64qf32_1.c: Likewise. + * gcc.target/arm/simd/vrev64qp16_1.c: Likewise. + * gcc.target/arm/simd/vrev64qp8_1.c: Likewise. + * gcc.target/arm/simd/vrev64qs16_1.c: Likewise. + * gcc.target/arm/simd/vrev64qs32_1.c: Likewise. + * gcc.target/arm/simd/vrev64qs8_1.c: Likewise. + * gcc.target/arm/simd/vrev64qu16_1.c: Likewise. + * gcc.target/arm/simd/vrev64qu32_1.c: Likewise. + * gcc.target/arm/simd/vrev64qu8_1.c: Likewise. + * gcc.target/arm/simd/vrev64s16_1.c: Likewise. + * gcc.target/arm/simd/vrev64s32_1.c: Likewise. + * gcc.target/arm/simd/vrev64s8_1.c: Likewise. + * gcc.target/arm/simd/vrev64u16_1.c: Likewise. + * gcc.target/arm/simd/vrev64u32_1.c: Likewise. + * gcc.target/arm/simd/vrev64u8_1.c: Likewise. + * gcc.target/arm/simd/vtrnf32_1.c: Likewise. + * gcc.target/arm/simd/vtrnp16_1.c: Likewise. + * gcc.target/arm/simd/vtrnp8_1.c: Likewise. + * gcc.target/arm/simd/vtrnqf32_1.c: Likewise. + * gcc.target/arm/simd/vtrnqp16_1.c: Likewise. + * gcc.target/arm/simd/vtrnqp8_1.c: Likewise. + * gcc.target/arm/simd/vtrnqs16_1.c: Likewise. + * gcc.target/arm/simd/vtrnqs32_1.c: Likewise. + * gcc.target/arm/simd/vtrnqs8_1.c: Likewise. + * gcc.target/arm/simd/vtrnqu16_1.c: Likewise. + * gcc.target/arm/simd/vtrnqu32_1.c: Likewise. + * gcc.target/arm/simd/vtrnqu8_1.c: Likewise. + * gcc.target/arm/simd/vtrns16_1.c: Likewise. + * gcc.target/arm/simd/vtrns32_1.c: Likewise. + * gcc.target/arm/simd/vtrns8_1.c: Likewise. + * gcc.target/arm/simd/vtrnu16_1.c: Likewise. + * gcc.target/arm/simd/vtrnu32_1.c: Likewise. + * gcc.target/arm/simd/vtrnu8_1.c: Likewise. + * gcc.target/arm/simd/vuzpf32_1.c: Likewise. + * gcc.target/arm/simd/vuzpp16_1.c: Likewise. + * gcc.target/arm/simd/vuzpp8_1.c: Likewise. + * gcc.target/arm/simd/vuzpqf32_1.c: Likewise. + * gcc.target/arm/simd/vuzpqp16_1.c: Likewise. + * gcc.target/arm/simd/vuzpqp8_1.c: Likewise. + * gcc.target/arm/simd/vuzpqs16_1.c: Likewise. + * gcc.target/arm/simd/vuzpqs32_1.c: Likewise. + * gcc.target/arm/simd/vuzpqs8_1.c: Likewise. + * gcc.target/arm/simd/vuzpqu16_1.c: Likewise. + * gcc.target/arm/simd/vuzpqu32_1.c: Likewise. + * gcc.target/arm/simd/vuzpqu8_1.c: Likewise. + * gcc.target/arm/simd/vuzps16_1.c: Likewise. + * gcc.target/arm/simd/vuzps32_1.c: Likewise. + * gcc.target/arm/simd/vuzps8_1.c: Likewise. + * gcc.target/arm/simd/vuzpu16_1.c: Likewise. + * gcc.target/arm/simd/vuzpu32_1.c: Likewise. + * gcc.target/arm/simd/vuzpu8_1.c: Likewise. + * gcc.target/arm/simd/vzipf32_1.c: Likewise. + * gcc.target/arm/simd/vzipp16_1.c: Likewise. + * gcc.target/arm/simd/vzipp8_1.c: Likewise. + * gcc.target/arm/simd/vzipqf32_1.c: Likewise. + * gcc.target/arm/simd/vzipqp16_1.c: Likewise. + * gcc.target/arm/simd/vzipqp8_1.c: Likewise. + * gcc.target/arm/simd/vzipqs16_1.c: Likewise. + * gcc.target/arm/simd/vzipqs32_1.c: Likewise. + * gcc.target/arm/simd/vzipqs8_1.c: Likewise. + * gcc.target/arm/simd/vzipqu16_1.c: Likewise. + * gcc.target/arm/simd/vzipqu32_1.c: Likewise. + * gcc.target/arm/simd/vzipqu8_1.c: Likewise. + * gcc.target/arm/simd/vzips16_1.c: Likewise. + * gcc.target/arm/simd/vzips32_1.c: Likewise. + * gcc.target/arm/simd/vzips8_1.c: Likewise. + * gcc.target/arm/simd/vzipu16_1.c: Likewise. + * gcc.target/arm/simd/vzipu32_1.c: Likewise. + * gcc.target/arm/simd/vzipu8_1.c: Likewise. + 2015-05-21 Sandra Loosemore * gcc.dg/vect/bb-slp-pr65935.c: Remove explicit "dg-do run". diff --git a/gcc/testsuite/gcc.target/arm/simd/simd.exp b/gcc/testsuite/gcc.target/arm/simd/simd.exp index 3afb537f27cb..fddf02faa4c5 100644 --- a/gcc/testsuite/gcc.target/arm/simd/simd.exp +++ b/gcc/testsuite/gcc.target/arm/simd/simd.exp @@ -27,9 +27,22 @@ load_lib gcc-dg.exp # Initialize `dg'. dg-init +# If the target hardware supports NEON, the default action is "run", otherwise +# just "compile". +global dg-do-what-default +set save-dg-do-what-default ${dg-do-what-default} +if {![check_effective_target_arm_neon_ok]} then { + return +} elseif {[is-effective-target arm_neon_hw]} then { + set dg-do-what-default run +} else { + set dg-do-what-default compile +} + # Main loop. dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ "" "" # All done. +set dg-do-what-default ${save-dg-do-what-default} dg-finish diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c index c1da6d38a5d7..41efba0b187b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c @@ -1,7 +1,5 @@ /* Test the `vextQf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c index adc086181b9c..643aa2f2c133 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c @@ -1,7 +1,5 @@ /* Test the `vextQp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c index e8b688da2b37..5cd1693fa47d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c @@ -1,6 +1,5 @@ /* Test the `vextQp64' ARM Neon intrinsic. */ -/* { dg-do run } */ /* { dg-require-effective-target arm_crypto_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_crypto } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c index 5f2cc53e3673..24fe651dfd99 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c @@ -1,7 +1,5 @@ /* Test the `vextQp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c index c0d791dcef3c..702da6cf0d93 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c @@ -1,7 +1,5 @@ /* Test the `vextQs16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c index ed5b21091cc3..b8dc896fd99a 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c @@ -1,7 +1,5 @@ /* Test the `vextQs32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c index dbbee47c58b3..a0a28a0ff9d2 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c @@ -1,7 +1,5 @@ /* Test the `vextQs64' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c index 0ebdce381656..ac905d8837f7 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c @@ -1,7 +1,5 @@ /* Test the `vextQs8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c index 136f2b8741fb..2b5bbf37985f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c @@ -1,7 +1,5 @@ /* Test the `vextQu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c index 66ce035c5a24..21a536a51483 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c @@ -1,7 +1,5 @@ /* Test the `vextQu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c index ebe4abd069f5..1f09987ebc24 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c @@ -1,7 +1,5 @@ /* Test the `vextQu64' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c index 432ac0a56748..ddc0911ec776 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c @@ -1,7 +1,5 @@ /* Test the `vextQu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c index 99e0bad0ed0b..d25a1ae03624 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c @@ -1,7 +1,5 @@ /* Test the `vextf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c index 00695bf64192..5312fde4ff5d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c @@ -1,7 +1,5 @@ /* Test the `vextp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c index 8783e166ea7c..2121fab901b7 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c @@ -1,6 +1,5 @@ /* Test the `vextp64' ARM Neon intrinsic. */ -/* { dg-do run } */ /* { dg-require-effective-target arm_crypto_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_crypto } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c index 2ba72c1ac0c1..544ac03ea6cf 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c @@ -1,7 +1,5 @@ /* Test the `vextp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c index 4fa57d6b696e..2e9e8912f762 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c @@ -1,7 +1,5 @@ /* Test the `vexts16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c index 3cd59360e28d..cca78e8481e0 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c @@ -1,7 +1,5 @@ /* Test the `vexts32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c index 10053a5e398e..0737ba21985a 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c @@ -1,7 +1,5 @@ /* Test the `vexts64' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c index 194e198b98e8..ed3f50be8f9d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c @@ -1,7 +1,5 @@ /* Test the `vexts8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c index f69c2bdc77fc..7d9cc51a1041 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c @@ -1,7 +1,5 @@ /* Test the `vextu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c index b76e383cadb1..48effc05bc62 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c @@ -1,7 +1,5 @@ /* Test the `vextu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c index eeb0be2732c0..b4d4f870d293 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c @@ -1,7 +1,5 @@ /* Test the `vextu64' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c index a9d62b31dffa..aacfb39f0c0e 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c @@ -1,7 +1,5 @@ /* Test the `vextu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O3 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c index fddb32fbb8bf..7eec89236b19 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev16p8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c index b4634b8dbdeb..073b7c4da84a 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev16q_p8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c index 691799b6b945..9d36c7af8ec3 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev16q_s8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c index f6ab4ac5cd1f..bbcf1717f078 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev16q_u8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c index 0a03721f29c7..f7d0f7af69f6 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev16s8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c index 7e5f54808ac7..e94b7089ace1 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev16u8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c index f3643fa96da9..b3d170210e9b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32p16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c index d823e59ff1c4..664cae83e690 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32p8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c index f8ba8a916ef6..0f462d07b23d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32q_p16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c index 0ddf6081a826..44f4be30c9e8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32q_p8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c index 30d0314c2020..8ad01ea1c27d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32q_s16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c index 03ddd2be25c6..b04959359f12 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32q_s8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c index 71765437b656..7c2602ac3bb3 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32q_u16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c index 403292c7cd84..0d98d19a2ed4 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32q_u8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c index e182ab988cef..8642c79f8bb8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32s16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c index a48c41551764..37411b13e83d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32s8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c index 076f8ab885b7..2293f499cf36 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32u16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c index 240d4596e8cc..5d7190513a3e 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev32u8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c index f5d3bcae5647..d393baf7321d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64f32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c index 8c685c0f8ca3..d61cdb8e8860 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64p16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c index 67ac1e491177..6ac5281f3bda 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64p8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c index 74130b7d8214..8e576a1f8c76 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_f32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c index 71f3b4ba4b7a..b60a005b58fa 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_p16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c index 324a738c660a..c50ea03e4428 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_p8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c index 9a373ec4100f..f294c2f277e3 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_s16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c index 0f10c6cb0780..f1c953f84242 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_s32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c index cf380143be62..42a59a025955 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_s8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c index 010d6dbb8057..14f576962b55 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_u16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c index 908769cc6827..8ad81e8355d8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_u32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c index 2fa07d129800..f094926d8369 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64q_u8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c index f14319c32148..d448e48c2dd7 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64s16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c index ead57225f3e6..8cfee433d287 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64s32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c index 29d684dcd1cd..685bfa34097b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64s8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c index feddacce2b59..7b8714891215 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64u16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c index 92a81f44041e..589d67806886 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64u32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c index f904af5ca77f..9bd14bd99a1a 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c @@ -1,7 +1,5 @@ /* Test the `vrev64u8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c index 0f9b6c9b8bd5..91be87149bd0 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c index 0ff43198109d..695c208a739e 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c index 2b047e4d7594..5124f61e1df7 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c index dd4e8836f3cf..bad97a5041bf 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c index 374eee396de2..26a6cf4c1d49 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c index b252fd5f3b0e..e883523ab3cf 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c index 5f06d2a3b128..19bbb48eca9b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQs16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c index 221175c46c60..348bd96b24e1 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQs32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c index 9352b37a7836..3b607181d35b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQs8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c index 7f40109b2a3f..e12bad130e02 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c index 1c61fc34f7c2..9d051204b94f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c index 82f911d5a78f..a59a908909d2 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnQu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c index af2c68f381f6..330af22eb33c 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c @@ -1,7 +1,5 @@ /* Test the `vtrns16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c index 35a98ea95514..b20a752afa73 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c @@ -1,7 +1,5 @@ /* Test the `vtrns32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c index 395015d1330a..ce268169b433 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c @@ -1,7 +1,5 @@ /* Test the `vtrns8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c index df0d963a5fad..a8343ae3b715 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c index 764ed623f07e..7d2f36d7eff7 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c index f5b4d68966ea..65521f9c4106 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c @@ -1,7 +1,5 @@ /* Test the `vtrnu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c index 723c86a16bee..845d20390cb5 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c index c7ad757b55e4..09226233b8fc 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c index 670b55067797..916e39615e67 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c index 53147f1a43e3..bcdf30378ed6 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c index feef15af27e7..4d3aeab30d9b 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c index db98f353354e..9288c4ba11bb 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c index 808d562732b8..9c7e10efdcd4 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQs16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c index 7adf5f9b91f1..60a79c91d509 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQs32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c index 9d0256a632a0..4757eac77037 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQs8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c index 23106edf529b..cb33d4a46168 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c index 0002fdfcbd96..ebaeea04ad8d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c index f8d19dc5582d..221cde604dc1 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpQu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c index 6e3f2eb118bd..77ccb47ffe9f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c @@ -1,7 +1,5 @@ /* Test the `vuzps16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c index 372c39387542..42a763bda6cf 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c @@ -1,7 +1,5 @@ /* Test the `vuzps32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c index 3338477778ee..5a9242e46b86 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c @@ -1,7 +1,5 @@ /* Test the `vuzps8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c index 378b5a9df911..b43df716f90d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c index ebb0d6b5fa63..0e746c88e13c 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c index 82719a503c42..fbdcec7d7236 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c @@ -1,7 +1,5 @@ /* Test the `vuzpu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c index efaa96ea9558..55cb956cf9f1 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c @@ -1,7 +1,5 @@ /* Test the `vzipf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c index 4154333a7f7a..7b674579dccd 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c @@ -1,7 +1,5 @@ /* Test the `vzipp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c index 9fe2384c9f90..8222857ea66f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c @@ -1,7 +1,5 @@ /* Test the `vzipp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c index 8c547a79f5b2..34f8afcefe3a 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQf32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c index e2af10b2af11..f0ef7feb2be5 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQp16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c index 11a13298563c..2e78311f61a4 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQp8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c index 0576c0033e6a..89ed05e9be3f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQs16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c index 6cf24396d200..9f4ed6e448fb 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQs32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c index 0244374e0013..9bb0d772fe16 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQs8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c index 3c406f514d2a..6a5b6a92244e 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c index ba1393c6c923..e46681ba4b8e 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c index 023ecac3a522..882169bd05fd 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c @@ -1,7 +1,5 @@ /* Test the `vzipQu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c index b6c3c2fe8976..5c2b680c9060 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c @@ -1,7 +1,5 @@ /* Test the `vzips16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c index 1a6f17093424..5deb49b76935 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c @@ -1,7 +1,5 @@ /* Test the `vzips32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c index 8569357817ba..69a1b65c9e2d 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c @@ -1,7 +1,5 @@ /* Test the `vzips8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c index 23bfcc4d962e..0c478963b0ec 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c @@ -1,7 +1,5 @@ /* Test the `vzipu16' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c index 6a753f25a9ca..8b666a3b38e4 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c @@ -1,7 +1,5 @@ /* Test the `vzipu32' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c index 972af74237f9..f7878a6986ad 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c @@ -1,7 +1,5 @@ /* Test the `vzipu8' ARM Neon intrinsic. */ -/* { dg-do run } */ -/* { dg-require-effective-target arm_neon_ok } */ /* { dg-options "-save-temps -O1 -fno-inline" } */ /* { dg-add-options arm_neon } */