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i386.md (splitters for int-float conversion): Use SUBREG_REG on SUBREGs in splitter constraints. 

* config/i386/i386.md (splitters for int-float conversion): Use
	SUBREG_REG on SUBREGs in splitter constraints.

From-SVN: r180748
This commit is contained in:
Uros Bizjak 2011-11-01 23:46:07 +01:00 committed by Uros Bizjak
parent f4496f0fec
commit a8b5c4e827
2 changed files with 28 additions and 10 deletions
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2
gcc/ChangeLog
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@ -5,7 +5,7 @@
2011-11-01 Uros Bizjak <ubizjak@gmail.com> 2011-11-01 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (splitters for int-float conversion): Use * config/i386/i386.md (splitters for int-float conversion): Use
reg_or_subregno in splitter constraints. SUBREG_REG on SUBREGs in splitter constraints.
2011-11-01 Jakub Jelinek <jakub@redhat.com> 2011-11-01 Jakub Jelinek <jakub@redhat.com>

36
gcc/config/i386/i386.md
View File

@ -4920,7 +4920,9 @@
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& TARGET_INTER_UNIT_CONVERSIONS && TARGET_INTER_UNIT_CONVERSIONS
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 0) (float:MODEF (match_dup 1)))]) [(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_split (define_split
@ -4931,7 +4933,9 @@
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (float:MODEF (match_dup 2)))]) (set (match_dup 0) (float:MODEF (match_dup 2)))])
@ -5020,7 +5024,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH "TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)] [(const_int 0)]
{ {
rtx op1 = operands[1]; rtx op1 = operands[1];
@ -5061,7 +5067,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH "TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)] [(const_int 0)]
{ {
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
@ -5083,7 +5091,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH "TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)] [(const_int 0)]
{ {
rtx op1 = operands[1]; rtx op1 = operands[1];
@ -5127,7 +5137,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH "TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)] [(const_int 0)]
{ {
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
@ -5188,7 +5200,9 @@
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 0) (float:MODEF (match_dup 1)))]) [(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit" (define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit"
@ -5221,7 +5235,9 @@
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (float:MODEF (match_dup 2)))]) (set (match_dup 0) (float:MODEF (match_dup 2)))])
@ -5232,7 +5248,9 @@
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT) "(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& reload_completed && reload_completed
&& SSE_REGNO_P (reg_or_subregno (operands[0]))" && (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
&& SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 0) (float:MODEF (match_dup 1)))]) [(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp" (define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp"