mirror of git://gcc.gnu.org/git/gcc.git
[AArch64][5/10] ARMv8.2-A FP16 lane vector intrinsics
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_mulx_elt_to_64v2df): Rename to
"*aarch64_mulx_elt_from_dup<mode>".
(*aarch64_mul3_elt<mode>): Update schedule type.
(*aarch64_mul3_elt_from_dup<mode>): Likewise.
(*aarch64_fma4_elt_from_dup<mode>): Likewise.
(*aarch64_fnma4_elt_from_dup<mode>): Likewise.
* config/aarch64/iterators.md (VMUL): Supprt half precision float modes.
(f, fp): Support HF modes.
* config/aarch64/arm_neon.h (vfma_lane_f16, vfmaq_lane_f16,
vfma_laneq_f16, vfmaq_laneq_f16, vfma_n_f16, vfmaq_n_f16, vfms_lane_f16,
vfmsq_lane_f16, vfms_laneq_f16, vfmsq_laneq_f16, vfms_n_f16,
vfmsq_n_f16, vmul_lane_f16, vmulq_lane_f16, vmul_laneq_f16,
vmulq_laneq_f16, vmul_n_f16, vmulq_n_f16, vmulx_lane_f16,
vmulxq_lane_f16, vmulx_laneq_f16, vmulxq_laneq_f16): New.
From-SVN: r238719
This commit is contained in:
Jiong Wang
Jiong Wang
parent
89ed6d5f5e
commit
ab2e8f01f1
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@ -1,3 +1,20 @@
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2016-07-25 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64-simd.md (*aarch64_mulx_elt_to_64v2df): Rename to
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"*aarch64_mulx_elt_from_dup<mode>".
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(*aarch64_mul3_elt<mode>): Update schedule type.
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(*aarch64_mul3_elt_from_dup<mode>): Likewise.
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(*aarch64_fma4_elt_from_dup<mode>): Likewise.
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(*aarch64_fnma4_elt_from_dup<mode>): Likewise.
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* config/aarch64/iterators.md (VMUL): Supprt half precision float modes.
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(f, fp): Support HF modes.
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* config/aarch64/arm_neon.h (vfma_lane_f16, vfmaq_lane_f16,
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vfma_laneq_f16, vfmaq_laneq_f16, vfma_n_f16, vfmaq_n_f16, vfms_lane_f16,
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vfmsq_lane_f16, vfms_laneq_f16, vfmsq_laneq_f16, vfms_n_f16,
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vfmsq_n_f16, vmul_lane_f16, vmulq_lane_f16, vmul_laneq_f16,
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vmulq_laneq_f16, vmul_n_f16, vmulq_n_f16, vmulx_lane_f16,
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vmulxq_lane_f16, vmulx_laneq_f16, vmulxq_laneq_f16): New.
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2016-07-25 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
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@ -351,7 +351,7 @@
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "<f>mul\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
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}
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[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
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[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
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)
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(define_insn "*aarch64_mul3_elt_<vswap_width_name><mode>"
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@ -379,7 +379,7 @@
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(match_operand:VMUL 2 "register_operand" "w")))]
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"TARGET_SIMD"
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"<f>mul\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]";
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[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
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[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
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)
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(define_insn "aarch64_rsqrte<mode>"
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@ -1634,7 +1634,7 @@
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(match_operand:VMUL 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
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[(set_attr "type" "neon<fp>_mla_<Vetype>_scalar<q>")]
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[(set_attr "type" "neon<fp>_mla_<stype>_scalar<q>")]
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)
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(define_insn "*aarch64_fma4_elt_to_64v2df"
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@ -1712,7 +1712,7 @@
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(match_operand:VMUL 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
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[(set_attr "type" "neon<fp>_mla_<Vetype>_scalar<q>")]
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[(set_attr "type" "neon<fp>_mla_<stype>_scalar<q>")]
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)
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(define_insn "*aarch64_fnma4_elt_to_64v2df"
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@ -3101,20 +3101,18 @@
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[(set_attr "type" "neon_fp_mul_<Vetype><q>")]
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)
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;; vmulxq_lane_f64
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;; vmulxq_lane
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(define_insn "*aarch64_mulx_elt_to_64v2df"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(unspec:V2DF
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[(match_operand:V2DF 1 "register_operand" "w")
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(vec_duplicate:V2DF
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(match_operand:DF 2 "register_operand" "w"))]
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(define_insn "*aarch64_mulx_elt_from_dup<mode>"
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[(set (match_operand:VHSDF 0 "register_operand" "=w")
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(unspec:VHSDF
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[(match_operand:VHSDF 1 "register_operand" "w")
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(vec_duplicate:VHSDF
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(match_operand:<VEL> 2 "register_operand" "w"))]
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UNSPEC_FMULX))]
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"TARGET_SIMD"
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{
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return "fmulx\t%0.2d, %1.2d, %2.d[0]";
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}
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[(set_attr "type" "neon_fp_mul_d_scalar_q")]
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"fmulx\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]";
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[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
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)
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;; vmulxs_lane_f32, vmulxs_laneq_f32
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@ -26773,6 +26773,160 @@ vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
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return __builtin_aarch64_fnmav8hf (__b, __c, __a);
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}
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/* ARMv8.2-A FP16 lane vector intrinsics. */
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vfma_lane_f16 (float16x4_t __a, float16x4_t __b,
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float16x4_t __c, const int __lane)
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{
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return vfma_f16 (__a, __b, __aarch64_vdup_lane_f16 (__c, __lane));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vfmaq_lane_f16 (float16x8_t __a, float16x8_t __b,
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float16x4_t __c, const int __lane)
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{
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return vfmaq_f16 (__a, __b, __aarch64_vdupq_lane_f16 (__c, __lane));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vfma_laneq_f16 (float16x4_t __a, float16x4_t __b,
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float16x8_t __c, const int __lane)
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{
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return vfma_f16 (__a, __b, __aarch64_vdup_laneq_f16 (__c, __lane));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vfmaq_laneq_f16 (float16x8_t __a, float16x8_t __b,
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float16x8_t __c, const int __lane)
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{
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return vfmaq_f16 (__a, __b, __aarch64_vdupq_laneq_f16 (__c, __lane));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vfma_n_f16 (float16x4_t __a, float16x4_t __b, float16_t __c)
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{
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return vfma_f16 (__a, __b, vdup_n_f16 (__c));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
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{
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return vfmaq_f16 (__a, __b, vdupq_n_f16 (__c));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vfms_lane_f16 (float16x4_t __a, float16x4_t __b,
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float16x4_t __c, const int __lane)
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{
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return vfms_f16 (__a, __b, __aarch64_vdup_lane_f16 (__c, __lane));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vfmsq_lane_f16 (float16x8_t __a, float16x8_t __b,
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float16x4_t __c, const int __lane)
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{
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return vfmsq_f16 (__a, __b, __aarch64_vdupq_lane_f16 (__c, __lane));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vfms_laneq_f16 (float16x4_t __a, float16x4_t __b,
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float16x8_t __c, const int __lane)
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{
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return vfms_f16 (__a, __b, __aarch64_vdup_laneq_f16 (__c, __lane));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vfmsq_laneq_f16 (float16x8_t __a, float16x8_t __b,
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float16x8_t __c, const int __lane)
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{
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return vfmsq_f16 (__a, __b, __aarch64_vdupq_laneq_f16 (__c, __lane));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vfms_n_f16 (float16x4_t __a, float16x4_t __b, float16_t __c)
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{
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return vfms_f16 (__a, __b, vdup_n_f16 (__c));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vfmsq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
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{
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return vfmsq_f16 (__a, __b, vdupq_n_f16 (__c));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vmul_lane_f16 (float16x4_t __a, float16x4_t __b, const int __lane)
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{
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return vmul_f16 (__a, vdup_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vmulq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __lane)
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{
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return vmulq_f16 (__a, vdupq_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vmul_laneq_f16 (float16x4_t __a, float16x8_t __b, const int __lane)
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{
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return vmul_f16 (__a, vdup_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vmulq_laneq_f16 (float16x8_t __a, float16x8_t __b, const int __lane)
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{
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return vmulq_f16 (__a, vdupq_n_f16 (__aarch64_vget_lane_any (__b, __lane)));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vmul_n_f16 (float16x4_t __a, float16_t __b)
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{
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return vmul_lane_f16 (__a, vdup_n_f16 (__b), 0);
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vmulq_n_f16 (float16x8_t __a, float16_t __b)
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{
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return vmulq_laneq_f16 (__a, vdupq_n_f16 (__b), 0);
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vmulx_lane_f16 (float16x4_t __a, float16x4_t __b, const int __lane)
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{
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return vmulx_f16 (__a, __aarch64_vdup_lane_f16 (__b, __lane));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vmulxq_lane_f16 (float16x8_t __a, float16x4_t __b, const int __lane)
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{
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return vmulxq_f16 (__a, __aarch64_vdupq_lane_f16 (__b, __lane));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vmulx_laneq_f16 (float16x4_t __a, float16x8_t __b, const int __lane)
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{
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return vmulx_f16 (__a, __aarch64_vdup_laneq_f16 (__b, __lane));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vmulxq_laneq_f16 (float16x8_t __a, float16x8_t __b, const int __lane)
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{
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return vmulxq_f16 (__a, __aarch64_vdupq_laneq_f16 (__b, __lane));
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}
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__extension__ static __inline float16x4_t __attribute__ ((__always_inline__))
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vmulx_n_f16 (float16x4_t __a, float16_t __b)
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{
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return vmulx_f16 (__a, vdup_n_f16 (__b));
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}
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__extension__ static __inline float16x8_t __attribute__ ((__always_inline__))
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vmulxq_n_f16 (float16x8_t __a, float16_t __b)
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{
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return vmulxq_f16 (__a, vdupq_n_f16 (__b));
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}
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#pragma GCC pop_options
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#undef __aarch64_vget_lane_any
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@ -218,7 +218,10 @@
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(define_mode_iterator DX [DI DF])
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;; Modes available for <f>mul lane operations.
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(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
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(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
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(V4HF "TARGET_SIMD_F16INST")
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(V8HF "TARGET_SIMD_F16INST")
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V2SF V4SF V2DF])
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;; Modes available for <f>mul lane operations changing lane count.
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(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
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@ -730,6 +733,7 @@
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(V4HI "") (V8HI "")
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(V2SI "") (V4SI "")
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(DI "") (V2DI "")
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(V4HF "f") (V8HF "f")
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(V2SF "f") (V4SF "f")
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(V2DF "f") (DF "f")])
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@ -738,6 +742,7 @@
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(V4HI "") (V8HI "")
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(V2SI "") (V4SI "")
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(DI "") (V2DI "")
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(V4HF "_fp") (V8HF "_fp")
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(V2SF "_fp") (V4SF "_fp")
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(V2DF "_fp") (DF "_fp")
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(SF "_fp")])
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