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arm.md (arm_andsi3_insn): Add alternatives for 16-bit encoding. 

2013-07-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.md (arm_andsi3_insn): Add alternatives for 16-bit
	encoding.
	(iorsi3_insn): Likewise.
	(arm_xorsi3): Likewise.

From-SVN: r200593
This commit is contained in:
Kyrylo Tkachov 2013-07-02 10:21:36 +00:00 committed by Kyrylo Tkachov
parent 4bc21884b4
commit afc5e8a6a7
2 changed files with 31 additions and 17 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2013-07-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (arm_andsi3_insn): Add alternatives for 16-bit
encoding.
(iorsi3_insn): Likewise.
(arm_xorsi3): Likewise.
2013-07-01 Sofiane Naci <sofiane.naci@arm.com> 2013-07-01 Sofiane Naci <sofiane.naci@arm.com>
* arm.md (attribute "wtype"): Delete. Move attribute values from here * arm.md (attribute "wtype"): Delete. Move attribute values from here

39
gcc/config/arm/arm.md
View File

@ -2564,11 +2564,12 @@
; ??? Check split length for Thumb-2 ; ??? Check split length for Thumb-2
(define_insn_and_split "*arm_andsi3_insn" (define_insn_and_split "*arm_andsi3_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r")
(and:SI (match_operand:SI 1 "s_register_operand" "r,r,r,r") (and:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r")
(match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "@
and%?\\t%0, %1, %2
and%?\\t%0, %1, %2 and%?\\t%0, %1, %2
bic%?\\t%0, %1, #%B2 bic%?\\t%0, %1, #%B2
and%?\\t%0, %1, %2 and%?\\t%0, %1, %2
@ -2583,9 +2584,11 @@
INTVAL (operands[2]), operands[0], operands[1], 0); INTVAL (operands[2]), operands[0], operands[1], 0);
DONE; DONE;
" "
[(set_attr "length" "4,4,4,16") [(set_attr "length" "4,4,4,4,16")
(set_attr "predicable" "yes") (set_attr "predicable" "yes")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*,simple_alu_imm")] (set_attr "predicable_short_it" "no,yes,no,no,no")
(set_attr "type"
"simple_alu_imm,simple_alu_imm,*,*,simple_alu_imm")]
) )
(define_insn "*thumb1_andsi3_insn" (define_insn "*thumb1_andsi3_insn"
@ -3338,11 +3341,12 @@
) )
(define_insn_and_split "*iorsi3_insn" (define_insn_and_split "*iorsi3_insn"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r,r")
(ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r,r") (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r,r")
(match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] (match_operand:SI 2 "reg_or_int_operand" "I,l,K,r,?n")))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "@
orr%?\\t%0, %1, %2
orr%?\\t%0, %1, %2 orr%?\\t%0, %1, %2
orn%?\\t%0, %1, #%B2 orn%?\\t%0, %1, #%B2
orr%?\\t%0, %1, %2 orr%?\\t%0, %1, %2
@ -3357,10 +3361,11 @@
INTVAL (operands[2]), operands[0], operands[1], 0); INTVAL (operands[2]), operands[0], operands[1], 0);
DONE; DONE;
} }
[(set_attr "length" "4,4,4,16") [(set_attr "length" "4,4,4,4,16")
(set_attr "arch" "32,t2,32,32") (set_attr "arch" "32,t2,t2,32,32")
(set_attr "predicable" "yes") (set_attr "predicable" "yes")
(set_attr "type" "simple_alu_imm,simple_alu_imm,*,*")] (set_attr "predicable_short_it" "no,yes,no,no,no")
(set_attr "type" "simple_alu_imm,*,simple_alu_imm,*,*")]
) )
(define_insn "*thumb1_iorsi3_insn" (define_insn "*thumb1_iorsi3_insn"
@ -3512,11 +3517,12 @@
) )
(define_insn_and_split "*arm_xorsi3" (define_insn_and_split "*arm_xorsi3"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r") [(set (match_operand:SI 0 "s_register_operand" "=r,l,r,r")
(xor:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") (xor:SI (match_operand:SI 1 "s_register_operand" "%r,0,r,r")
(match_operand:SI 2 "reg_or_int_operand" "I,r,?n")))] (match_operand:SI 2 "reg_or_int_operand" "I,l,r,?n")))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "@
eor%?\\t%0, %1, %2
eor%?\\t%0, %1, %2 eor%?\\t%0, %1, %2
eor%?\\t%0, %1, %2 eor%?\\t%0, %1, %2
#" #"
@ -3529,9 +3535,10 @@
INTVAL (operands[2]), operands[0], operands[1], 0); INTVAL (operands[2]), operands[0], operands[1], 0);
DONE; DONE;
} }
[(set_attr "length" "4,4,16") [(set_attr "length" "4,4,4,16")
(set_attr "predicable" "yes") (set_attr "predicable" "yes")
(set_attr "type" "simple_alu_imm,*,*")] (set_attr "predicable_short_it" "no,yes,no,no")
(set_attr "type" "simple_alu_imm,*,*,*")]
) )
(define_insn "*thumb1_xorsi3_insn" (define_insn "*thumb1_xorsi3_insn"