mirror of git://gcc.gnu.org/git/gcc.git
AArch64: convert widen_sum optabs to convert [PR122069]
This patch is a mechanical rewrite of the widen_[us]sum optabs from a direct to a conversion optab. The result of which requires the output mode to be added to the existing patterns. No change in functionality is expected. gcc/ChangeLog: PR middle-end/122069 * config/aarch64/aarch64-simd.md (widen_ssum<mode>3): Change into.. (widen_ssum<Vdblw><mode>3, widen_ssum<Vwide><mode>3): ... these. (widen_usum<mode>3): Change into ... (widen_usum<Vdblw><mode>3, widen_usum<Vwide><mode>3): ... these. * config/aarch64/iterators.md (Vdblw): New. (Vwide): Extend to match VWIDE. gcc/testsuite/ChangeLog: PR middle-end/122069 * gcc.target/aarch64/pr122069_1.c: New test. * gcc.target/aarch64/pr122069_2.c: New test.
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Tamar Christina
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@ -4647,7 +4647,7 @@
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;; <su><addsub>w<q>.
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(define_expand "widen_ssum<mode>3"
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(define_expand "widen_ssum<Vdblw><mode>3"
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[(set (match_operand:<VDBLW> 0 "register_operand")
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(plus:<VDBLW> (sign_extend:<VDBLW>
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(match_operand:VQW 1 "register_operand"))
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@ -4664,7 +4664,7 @@
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}
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)
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(define_expand "widen_ssum<mode>3"
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(define_expand "widen_ssum<Vwide><mode>3"
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[(set (match_operand:<VWIDE> 0 "register_operand")
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(plus:<VWIDE> (sign_extend:<VWIDE>
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(match_operand:VD_BHSI 1 "register_operand"))
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@ -4675,7 +4675,7 @@
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DONE;
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})
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(define_expand "widen_usum<mode>3"
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(define_expand "widen_usum<Vdblw><mode>3"
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[(set (match_operand:<VDBLW> 0 "register_operand")
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(plus:<VDBLW> (zero_extend:<VDBLW>
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(match_operand:VQW 1 "register_operand"))
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@ -4692,7 +4692,7 @@
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}
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)
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(define_expand "widen_usum<mode>3"
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(define_expand "widen_usum<Vwide><mode>3"
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[(set (match_operand:<VWIDE> 0 "register_operand")
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(plus:<VWIDE> (zero_extend:<VWIDE>
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(match_operand:VD_BHSI 1 "register_operand"))
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@ -1901,6 +1901,11 @@
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(V4HI "V2SI") (V8HI "V4SI")
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(V2SI "DI") (V4SI "V2DI")])
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;; Modes with double-width elements.
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(define_mode_attr Vdblw [(V8QI "v4hi") (V16QI "v8hi")
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(V4HI "v2si") (V8HI "v4si")
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(V2SI "di") (V4SI "v2di")])
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(define_mode_attr VQUADW [(V8QI "V4SI") (V16QI "V8SI")
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(V4HI "V2DI") (V8HI "V4DI")])
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@ -2003,7 +2008,9 @@
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(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
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;; Widened modes of vector modes, lowercase
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(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
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(define_mode_attr Vwide [(V2SI "v2di") (V4HI "v4si")
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(V2SF "v2df") (V4HF "v4sf")
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(V8QI "v8hi")
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(VNx16QI "vnx8hi") (VNx8HI "vnx4si")
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(VNx4SI "vnx2di")
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(VNx8HF "vnx4sf") (VNx4SF "vnx2df")
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@ -0,0 +1,46 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=armv8-a -mautovec-preference=asimd-only --param vect-epilogues-nomask=0 -fno-schedule-insns -fno-reorder-blocks -fno-schedule-insns2 -fdump-tree-vect-details" }*/
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/* { dg-final { check-function-bodies "**" "" } } */
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inline char char_abs(char i) {
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return (i < 0 ? -i : i);
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}
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/*
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** foo_int:
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** ...
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** sub v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b
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** zip1 v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b
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** zip2 v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b
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** uaddw v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4h
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** uaddw2 v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.8h
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** uaddw v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4h
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** uaddw2 v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.8h
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** ...
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*/
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int foo_int(unsigned char *x, unsigned char * restrict y) {
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int sum = 0;
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for (int i = 0; i < 8000; i++)
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sum += char_abs(x[i] - y[i]);
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return sum;
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}
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/*
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** foo2_int:
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** ...
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** add v[0-9]+.8h, v[0-9]+.8h, v[0-9]+.8h
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** uaddw v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.4h
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** uaddw2 v[0-9]+.4s, v[0-9]+.4s, v[0-9]+.8h
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** ...
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*/
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int foo2_int(unsigned short *x, unsigned short * restrict y) {
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int sum = 0;
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for (int i = 0; i < 8000; i++)
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{
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x[i] = x[i] + y[i];
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sum += x[i];
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}
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return sum;
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}
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/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */
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@ -0,0 +1,80 @@
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/* { dg-do run } */
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/* { dg-options "-O3 -march=armv8-a -mautovec-preference=asimd-only -fdump-tree-vect-details" }*/
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inline char char_abs(char i) {
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return (i < 0 ? -i : i);
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}
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__attribute__((noipa))
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int foo_int(unsigned char *x, unsigned char * restrict y) {
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int sum = 0;
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for (int i = 0; i < 100; i++)
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sum += char_abs(x[i] - y[i]);
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return sum;
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}
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__attribute__((noipa))
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int foo2_int(unsigned short *x, unsigned short * restrict y,
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unsigned short * restrict z) {
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int sum = 0;
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for (int i = 0; i < 100; i++)
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{
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z[i] = x[i] + y[i];
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sum += z[i];
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}
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return sum;
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}
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__attribute__((noipa))
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int foo_int2(unsigned char *x, unsigned char * restrict y) {
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int sum = 0;
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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sum += char_abs(x[i] - y[i]);
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return sum;
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}
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__attribute__((noipa))
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int foo2_int2(unsigned short *x, unsigned short * restrict y,
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unsigned short * restrict z) {
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int sum = 0;
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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{
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z[i] = x[i] + y[i];
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sum += z[i];
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}
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return sum;
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}
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int main ()
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{
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unsigned short a[100];
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unsigned short b[100];
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unsigned short r1[100];
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unsigned short r2[100];
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unsigned char c[100];
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unsigned char d[100];
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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{
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a[i] = c[i] = i;
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b[i] = d[i] = 100 - i;
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}
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if (foo_int (c, d) != foo_int2 (c, d))
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__builtin_abort();
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if (foo2_int (a, b, r1) != foo2_int2 (a, b, r2))
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__builtin_abort();
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#pragma GCC novector
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for (int i = 0; i < 100; i++)
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if (r1[i] != r2[i])
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__builtin_abort ();
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return 0;
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}
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/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */
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