mirror of git://gcc.gnu.org/git/gcc.git
re PR target/56315 (ARM: Improve use of 64-bit constants in logical operations)
gcc/ 2013-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/56315 * config/arm/arm.c (const_ok_for_dimode_op): Handle IOR. * config/arm/arm.md (*iordi3_insn): Change to insn_and_split. * config/arm/neon.md (iordi3_neon): Remove. (neon_vorr<mode>): Generate iordi3 instead of iordi3_neon. * config/arm/predicates.md (imm_for_neon_logic_operand): Move to earlier in the file. (neon_logic_op2): Likewise. (arm_iordi_operand_neon): New predicate. gcc/testsuite/ 2013-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com> PR target/56315 * gcc.target/arm/iordi3-opt.c: New test. From-SVN: r199527
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Kyrylo Tkachov
Kyrylo Tkachov
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b6af05a9b3
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@ -1,3 +1,15 @@
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2013-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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PR target/56315
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* config/arm/arm.c (const_ok_for_dimode_op): Handle IOR.
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* config/arm/arm.md (*iordi3_insn): Change to insn_and_split.
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* config/arm/neon.md (iordi3_neon): Remove.
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(neon_vorr<mode>): Generate iordi3 instead of iordi3_neon.
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* config/arm/predicates.md (imm_for_neon_logic_operand):
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Move to earlier in the file.
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(neon_logic_op2): Likewise.
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(arm_iordi_operand_neon): New predicate.
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2013-05-31 Richard Biener <rguenther@suse.de>
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PR tree-optimization/57478
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@ -2677,6 +2677,7 @@ const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code)
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switch (code)
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{
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case AND:
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case IOR:
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return (const_ok_for_op (hi_val, code) || hi_val == 0xFFFFFFFF)
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&& (const_ok_for_op (lo_val, code) || lo_val == 0xFFFFFFFF);
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case PLUS:
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@ -2997,14 +2997,47 @@
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""
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)
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(define_insn "*iordi3_insn"
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[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
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(ior:DI (match_operand:DI 1 "s_register_operand" "%0,r")
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(match_operand:DI 2 "s_register_operand" "r,r")))]
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"TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
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"#"
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[(set_attr "length" "8")
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(set_attr "predicable" "yes")]
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(define_insn_and_split "*iordi3_insn"
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[(set (match_operand:DI 0 "s_register_operand" "=w,w ,&r,&r,&r,&r,?w,?w")
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(ior:DI (match_operand:DI 1 "s_register_operand" "%w,0 ,0 ,r ,0 ,r ,w ,0")
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(match_operand:DI 2 "arm_iordi_operand_neon" "w ,Dl,r ,r ,De,De,w ,Dl")))]
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"TARGET_32BIT && !TARGET_IWMMXT"
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{
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switch (which_alternative)
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{
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case 0: /* fall through */
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case 6: return "vorr\t%P0, %P1, %P2";
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case 1: /* fall through */
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case 7: return neon_output_logic_immediate ("vorr", &operands[2],
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DImode, 0, VALID_NEON_QREG_MODE (DImode));
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case 2:
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case 3:
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case 4:
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case 5:
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return "#";
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default: gcc_unreachable ();
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}
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}
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"TARGET_32BIT && !TARGET_IWMMXT && reload_completed
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&& !(IS_VFP_REGNUM (REGNO (operands[0])))"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 5) (match_dup 6))]
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"
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{
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operands[3] = gen_lowpart (SImode, operands[0]);
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operands[5] = gen_highpart (SImode, operands[0]);
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operands[4] = simplify_gen_binary (IOR, SImode,
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gen_lowpart (SImode, operands[1]),
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gen_lowpart (SImode, operands[2]));
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operands[6] = simplify_gen_binary (IOR, SImode,
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gen_highpart (SImode, operands[1]),
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gen_highpart_mode (SImode, DImode, operands[2]));
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}"
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[(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,*,*,neon_int_1,neon_int_1")
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(set_attr "length" "*,*,8,8,8,8,8,8")
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(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
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)
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(define_insn "*iordi_zesidi_di"
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@ -679,29 +679,6 @@
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[(set_attr "neon_type" "neon_int_1")]
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)
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(define_insn "iordi3_neon"
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[(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r,?w,?w")
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(ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r,w,0")
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(match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r,w,Dl")))]
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"TARGET_NEON"
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{
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switch (which_alternative)
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{
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case 0: /* fall through */
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case 4: return "vorr\t%P0, %P1, %P2";
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case 1: /* fall through */
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case 5: return neon_output_logic_immediate ("vorr", &operands[2],
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DImode, 0, VALID_NEON_QREG_MODE (DImode));
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case 2: return "#";
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case 3: return "#";
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default: gcc_unreachable ();
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}
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}
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[(set_attr "neon_type" "neon_int_1,neon_int_1,*,*,neon_int_1,neon_int_1")
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(set_attr "length" "*,*,8,8,*,*")
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(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")]
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)
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;; The concrete forms of the Neon immediate-logic instructions are vbic and
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;; vorr. We support the pseudo-instruction vand instead, because that
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;; corresponds to the canonical form the middle-end expects to use for
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@ -5617,7 +5594,7 @@
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(match_operand:SI 3 "immediate_operand" "")]
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"TARGET_NEON"
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{
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emit_insn (gen_ior<mode>3<V_suf64> (operands[0], operands[1], operands[2]));
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emit_insn (gen_ior<mode>3 (operands[0], operands[1], operands[2]));
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DONE;
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})
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@ -42,6 +42,17 @@
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(ior (match_operand 0 "imm_for_neon_inv_logic_operand")
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(match_operand 0 "s_register_operand")))
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(define_predicate "imm_for_neon_logic_operand"
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(match_code "const_vector")
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{
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return (TARGET_NEON
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&& neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
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})
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(define_predicate "neon_logic_op2"
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(ior (match_operand 0 "imm_for_neon_logic_operand")
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(match_operand 0 "s_register_operand")))
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;; Any hard register.
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(define_predicate "arm_hard_register_operand"
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(match_code "reg")
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@ -162,6 +173,12 @@
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(match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))
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(match_operand 0 "neon_inv_logic_op2")))
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(define_predicate "arm_iordi_operand_neon"
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(ior (match_operand 0 "s_register_operand")
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(and (match_code "const_int")
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(match_test "const_ok_for_dimode_op (INTVAL (op), IOR)"))
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(match_operand 0 "neon_logic_op2")))
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(define_predicate "arm_adddi_operand"
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(ior (match_operand 0 "s_register_operand")
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(and (match_code "const_int")
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@ -535,17 +552,6 @@
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(ior (match_operand 0 "s_register_operand")
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(match_operand 0 "imm_for_neon_rshift_operand")))
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(define_predicate "imm_for_neon_logic_operand"
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(match_code "const_vector")
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{
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return (TARGET_NEON
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&& neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
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})
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(define_predicate "neon_logic_op2"
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(ior (match_operand 0 "imm_for_neon_logic_operand")
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(match_operand 0 "s_register_operand")))
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;; Predicates for named expanders that overlap multiple ISAs.
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(define_predicate "cmpdi_operand"
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@ -1,3 +1,8 @@
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2013-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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PR target/56315
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* gcc.target/arm/iordi3-opt.c: New test.
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2013-05-31 Janus Weil <janus@gcc.gnu.org>
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PR fortran/54190
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@ -0,0 +1,9 @@
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/* { dg-do compile } */
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/* { dg-options "-O1" } */
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unsigned long long or64 (unsigned long long input)
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{
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return input | 0x200000004ULL;
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}
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/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */
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