mirror of git://gcc.gnu.org/git/gcc.git
xtensa: Change the splitting of D[IF]mode constant assignments to be implemented in xt_largeconst instead of define_split
This patch moves the process of splitting D[IF]mode constant assignments into SImode ones from the define_split implementation after reloading to processing within the "xt_largeconst" target-specific pass. It also converts SFmode constant assignments into bit-equivalent SImode ones. This allows these assignments to be processed by the "constantsynth" optimization, which will be reimplemented later. gcc/ChangeLog: * config/xtensa/xtensa-protos.h (xtensa_split_DI_reg_imm): Remove. * config/xtensa/xtensa.cc (xtensa_split_DI_reg_imm): Remove. (split_DI_SF_DF_const): New worker function. (do_largeconst): Add a call to split_DI_SF_DF_const() to the insn enumeration loop. * config/xtensa/xtensa.md (movdi): Remove split code when the source is constant. (movdi_internal): Add a new constraint pair (a, Y) to the second of the existing constraint alternatives. (The auxiliary define_split for movdi_internal): Remove.
This commit is contained in:
Takayuki 'January June' Suwa
Max Filippov
parent
4864f24c86
commit
b6af5f46e3
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@ -59,7 +59,6 @@ extern char *xtensa_emit_sibcall (int, rtx *);
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extern bool xtensa_tls_referenced_p (rtx);
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extern enum rtx_code xtensa_shlrd_which_direction (rtx, rtx);
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extern bool xtensa_postreload_completed_p (void);
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extern void xtensa_split_DI_reg_imm (rtx *);
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extern char *xtensa_bswapsi2_output (rtx_insn *, const char *);
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#ifdef TREE_CODE
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@ -2633,27 +2633,6 @@ xtensa_postreload_completed_p (void)
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}
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/* Split a DImode pair of reg (operand[0]) and const_int (operand[1]) into
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two SImode pairs, the low-part (operands[0] and [1]) and the high-part
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(operands[2] and [3]). */
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void
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xtensa_split_DI_reg_imm (rtx *operands)
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{
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rtx lowpart, highpart;
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if (WORDS_BIG_ENDIAN)
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split_double (operands[1], &highpart, &lowpart);
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else
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split_double (operands[1], &lowpart, &highpart);
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operands[3] = highpart;
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operands[2] = gen_highpart (SImode, operands[0]);
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operands[1] = lowpart;
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operands[0] = gen_lowpart (SImode, operands[0]);
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}
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/* Return the asm output string of bswapsi2_internal insn pattern.
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It does this by scanning backwards for the BB from the specified insn,
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and if an another bswapsi2_internal is found, it omits the instruction
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@ -5892,6 +5871,102 @@ FPreg_neg_scaled_simm12b (rtx_insn *insn)
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return false;
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}
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/* Split DI/SF/DFmode constant assignments into pairs of SImode ones. This
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is also the pre-processing for constantsynth optimization that follows
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immediately after.
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Note that all constant values and assignments are treated as SImode
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because:
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- Synthesis methods rely on SImode operations
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- SImode assignments may be shorter
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- More opportunity for sharing literal pool entries
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This behavior would be acceptable if TARGET_CAN_CHANGE_MODE_CLASS always
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returned true (the current and default configuration). */
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static bool
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split_DI_SF_DF_const (rtx_insn *insn)
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{
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rtx pat, dest, src, dest0, dest1, src0, src1, src0c, src1c;
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int regno;
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if (GET_CODE (pat = PATTERN (insn)) != SET
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|| ! REG_P (dest = SET_DEST (pat)) || ! GP_REG_P (regno = REGNO (dest)))
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return false;
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/* It is more efficient to assign SFmode literal constants using their
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bit-equivalent SImode ones, thus we convert them so. */
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src = avoid_constant_pool_reference (SET_SRC (pat));
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if (GET_MODE (dest) == SFmode
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&& CONST_DOUBLE_P (src) && GET_MODE (src) == SFmode)
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{
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long l;
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REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (src), l);
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src0 = GEN_INT ((int32_t)l), dest0 = gen_rtx_REG (SImode, regno);
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if (dump_file)
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{
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fputs ("split_DI_SF_DF_const: ", dump_file);
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dump_value_slim (dump_file, src, 0);
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fprintf (dump_file,
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"f -> " HOST_WIDE_INT_PRINT_DEC " ("
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HOST_WIDE_INT_PRINT_HEX ")\n",
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INTVAL (src0), INTVAL (src0));
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}
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src0c = NULL_RTX;
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if (!TARGET_CONST16 && !TARGET_AUTO_LITPOOLS
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&& ! xtensa_simm12b (INTVAL (src0)))
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src0c = src0, src0 = force_const_mem (SImode, src0);
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remove_reg_equal_equiv_notes (insn);
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validate_change (insn, &PATTERN (insn), gen_rtx_SET (dest0, src0), 0);
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if (src0c)
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add_reg_note (insn, REG_EQUIV, copy_rtx (src0c));
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return true;
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}
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/* Splitting a D[IF]mode literal constant into two with split_double()
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results in a pair of CONST_INTs, so they are assigned in SImode
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regardless of the original source mode. */
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if ((GET_MODE (dest) == DImode && CONST_INT_P (src))
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|| (GET_MODE (dest) == DFmode
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&& CONST_DOUBLE_P (src) && GET_MODE (src) == DFmode))
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{
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dest0 = gen_rtx_REG (SImode, regno);
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dest1 = gen_rtx_REG (SImode, regno + 1);
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split_double (src, &src0, &src1);
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if (dump_file)
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{
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fputs ("split_DI_SF_DF_const: ", dump_file);
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dump_value_slim (dump_file, src, 0);
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fprintf (dump_file,
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" -> " HOST_WIDE_INT_PRINT_DEC " ("
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HOST_WIDE_INT_PRINT_HEX "), "
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HOST_WIDE_INT_PRINT_DEC " ("
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HOST_WIDE_INT_PRINT_HEX ")\n",
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INTVAL (src0), INTVAL (src0),
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INTVAL (src1), INTVAL (src1));
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}
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src1c = src0c = NULL_RTX;
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if (!TARGET_CONST16 && !TARGET_AUTO_LITPOOLS)
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{
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if (! xtensa_simm12b (INTVAL (src0)))
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src0c = src0, src0 = force_const_mem (SImode, src0);
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if (! xtensa_simm12b (INTVAL (src1)))
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src1c = src1, src1 = force_const_mem (SImode, src1);
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}
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remove_reg_equal_equiv_notes (insn);
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validate_change (insn, &PATTERN (insn), gen_rtx_SET (dest0, src0), 0);
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if (src0c)
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add_reg_note (insn, REG_EQUIV, copy_rtx (src0c));
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insn = emit_insn_after (gen_rtx_SET (dest1, src1), insn);
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if (src1c)
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add_reg_note (insn, REG_EQUIV, copy_rtx (src1c));
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return true;
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}
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return false;
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}
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/* Replace the source of [SH]Imode allocation whose value does not fit
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into signed 12 bits with a reference to litpool entry. */
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@ -5956,6 +6031,11 @@ do_largeconst (void)
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bool optimize_enabled = optimize && !optimize_debug;
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rtx_insn *insn;
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/* Verify the legitimacy of replacing constant assignments in
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DI/SF/DFmode with those in SImode. */
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gcc_assert (targetm.can_change_mode_class
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== hook_bool_mode_mode_reg_class_t_true);
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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if (NONJUMP_INSN_P (insn))
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{
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@ -5970,6 +6050,12 @@ do_largeconst (void)
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fit into signed 12 bits with a reference to litpool entry. */
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if (replacing_required)
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litpool_set_src (insn);
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/* Split DI/SF/DFmode constant assignments into pairs of SImode
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ones. This is also the pre-processing for constantsynth opti-
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mization that follows immediately after. */
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if (replacing_required)
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split_DI_SF_DF_const (insn);
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}
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}
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@ -1219,22 +1219,8 @@
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(match_operand:DI 1 "general_operand" ""))]
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""
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{
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if (CONSTANT_P (operands[1]))
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{
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/* Split in halves if 64-bit Const-to-Reg moves
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because of offering further optimization opportunities. */
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if (register_operand (operands[0], DImode))
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{
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rtx ops[4] = { operands[0], operands[1] };
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xtensa_split_DI_reg_imm (ops);
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emit_move_insn (ops[0], ops[1]);
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emit_move_insn (ops[2], ops[3]);
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DONE;
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}
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if (!TARGET_CONST16)
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operands[1] = force_const_mem (DImode, operands[1]);
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}
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if (!TARGET_CONST16 && CONSTANT_P (operands[1]))
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operands[1] = force_const_mem (DImode, operands[1]);
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if (!register_operand (operands[0], DImode)
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&& !register_operand (operands[1], DImode))
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@ -1244,8 +1230,8 @@
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})
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(define_insn_and_split "movdi_internal"
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[(set (match_operand:DI 0 "nonimmed_operand" "=a,W,a,a,U")
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(match_operand:DI 1 "move_operand" "r,i,T,U,r"))]
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[(set (match_operand:DI 0 "nonimmed_operand" "=a,a,W,a,a,U")
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(match_operand:DI 1 "move_operand" "r,Y,i,T,U,r"))]
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"register_operand (operands[0], DImode)
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|| register_operand (operands[1], DImode)"
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"#"
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@ -1260,22 +1246,9 @@
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std::swap (operands[2], operands[3]);
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}
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}
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[(set_attr "type" "move,move,load,load,store")
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[(set_attr "type" "move,load,move,load,load,store")
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(set_attr "mode" "DI")
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(set_attr "length" "6,12,6,6,6")])
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(match_operand:DI 1 "const_int_operand"))]
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"!TARGET_CONST16
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&& ! xtensa_postreload_completed_p ()"
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[(set (match_dup 0)
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(match_dup 1))
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(set (match_dup 2)
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(match_dup 3))]
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{
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xtensa_split_DI_reg_imm (operands);
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})
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(set_attr "length" "6,6,12,6,6,6")])
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;; 32-bit Integer moves
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