mirror of git://gcc.gnu.org/git/gcc.git
aarch64-torture.exp: New file.
2018-12-17 Steve Ellcey <sellcey@cavium.com> * gcc.target/aarch64/torture/aarch64-torture.exp: New file. * gcc.target/aarch64/torture/simd-abi-1.c: New test. * gcc.target/aarch64/torture/simd-abi-2.c: Ditto. * gcc.target/aarch64/torture/simd-abi-3.c: Ditto. * gcc.target/aarch64/torture/simd-abi-4.c: Ditto. * gcc.target/aarch64/torture/simd-abi-5.c: Ditto. * gcc.target/aarch64/torture/simd-abi-6.c: Ditto. * gcc.target/aarch64/torture/simd-abi-7.c: Ditto. From-SVN: r267209
This commit is contained in:
Steve Ellcey
parent
a0d0b980f1
commit
ba1a78ffd9
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# Copyright (C) 2018 Free Software Foundation, Inc.
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with GCC; see the file COPYING3. If not see
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# <http://www.gnu.org/licenses/>.
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# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
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# optimization options.
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# Exit immediately if this isn't a Aarch64 target.
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if { ![istarget aarch64*-*-*] } then {
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return
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}
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# Load support procs.
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load_lib gcc-dg.exp
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# If a testcase doesn't have special options, use these.
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global DEFAULT_CFLAGS
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if ![info exists DEFAULT_CFLAGS] then {
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set DEFAULT_CFLAGS " -ansi -pedantic-errors"
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}
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# Initialize `dg'.
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dg-init
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# Main loop.
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gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] "" $DEFAULT_CFLAGS
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# All done.
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dg-finish
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/* { dg-do compile } */
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void __attribute__ ((aarch64_vector_pcs))
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f (void)
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{
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/* Clobber all fp/simd regs and verify that the correct ones are saved
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and restored in the prologue and epilogue of a SIMD function. */
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__asm__ __volatile__ ("" ::: "q0", "q1", "q2", "q3");
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__asm__ __volatile__ ("" ::: "q4", "q5", "q6", "q7");
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__asm__ __volatile__ ("" ::: "q8", "q9", "q10", "q11");
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__asm__ __volatile__ ("" ::: "q12", "q13", "q14", "q15");
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__asm__ __volatile__ ("" ::: "q16", "q17", "q18", "q19");
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__asm__ __volatile__ ("" ::: "q20", "q21", "q22", "q23");
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__asm__ __volatile__ ("" ::: "q24", "q25", "q26", "q27");
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__asm__ __volatile__ ("" ::: "q28", "q29", "q30", "q31");
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}
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/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
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/* { dg-final { scan-assembler {\sstp\tq10, q11} } } */
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/* { dg-final { scan-assembler {\sstp\tq12, q13} } } */
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/* { dg-final { scan-assembler {\sstp\tq14, q15} } } */
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/* { dg-final { scan-assembler {\sstp\tq16, q17} } } */
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/* { dg-final { scan-assembler {\sstp\tq18, q19} } } */
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/* { dg-final { scan-assembler {\sstp\tq20, q21} } } */
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/* { dg-final { scan-assembler {\sstp\tq22, q23} } } */
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/* { dg-final { scan-assembler {\sldp\tq8, q9} } } */
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/* { dg-final { scan-assembler {\sldp\tq10, q11} } } */
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/* { dg-final { scan-assembler {\sldp\tq12, q13} } } */
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/* { dg-final { scan-assembler {\sldp\tq14, q15} } } */
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/* { dg-final { scan-assembler {\sldp\tq16, q17} } } */
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/* { dg-final { scan-assembler {\sldp\tq18, q19} } } */
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/* { dg-final { scan-assembler {\sldp\tq20, q21} } } */
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/* { dg-final { scan-assembler {\sldp\tq22, q23} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\td} } } */
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/* { dg-final { scan-assembler-not {\sldp\td} } } */
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/* { dg-final { scan-assembler-not {\sstr\t} } } */
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/* { dg-final { scan-assembler-not {\sldr\t} } } */
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/* { dg-do compile } */
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void
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f (void)
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{
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/* Clobber all fp/simd regs and verify that the correct ones are saved
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and restored in the prologue and epilogue of a normal non-SIMD function. */
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__asm__ __volatile__ ("" ::: "q0", "q1", "q2", "q3");
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__asm__ __volatile__ ("" ::: "q4", "q5", "q6", "q7");
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__asm__ __volatile__ ("" ::: "q8", "q9", "q10", "q11");
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__asm__ __volatile__ ("" ::: "q12", "q13", "q14", "q15");
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__asm__ __volatile__ ("" ::: "q16", "q17", "q18", "q19");
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__asm__ __volatile__ ("" ::: "q20", "q21", "q22", "q23");
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__asm__ __volatile__ ("" ::: "q24", "q25", "q26", "q27");
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__asm__ __volatile__ ("" ::: "q28", "q29", "q30", "q31");
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}
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/* { dg-final { scan-assembler {\sstp\td8, d9} } } */
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/* { dg-final { scan-assembler {\sstp\td10, d11} } } */
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/* { dg-final { scan-assembler {\sstp\td12, d13} } } */
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/* { dg-final { scan-assembler {\sstp\td14, d15} } } */
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/* { dg-final { scan-assembler {\sldp\td8, d9} } } */
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/* { dg-final { scan-assembler {\sldp\td10, d11} } } */
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/* { dg-final { scan-assembler {\sldp\td12, d13} } } */
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/* { dg-final { scan-assembler {\sldp\td14, d15} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq[01234567]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq[01234567]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq1[6789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq1[6789]} } } */
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/* { dg-final { scan-assembler-not {\sstr\t} } } */
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/* { dg-final { scan-assembler-not {\sldr\t} } } */
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/* { dg-do compile } */
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extern void g (void);
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void __attribute__ ((aarch64_vector_pcs))
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f (void)
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{
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g();
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}
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/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
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/* { dg-final { scan-assembler {\sstp\tq10, q11} } } */
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/* { dg-final { scan-assembler {\sstp\tq12, q13} } } */
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/* { dg-final { scan-assembler {\sstp\tq14, q15} } } */
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/* { dg-final { scan-assembler {\sstp\tq16, q17} } } */
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/* { dg-final { scan-assembler {\sstp\tq18, q19} } } */
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/* { dg-final { scan-assembler {\sstp\tq20, q21} } } */
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/* { dg-final { scan-assembler {\sstp\tq22, q23} } } */
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/* { dg-final { scan-assembler {\sldp\tq8, q9} } } */
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/* { dg-final { scan-assembler {\sldp\tq10, q11} } } */
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/* { dg-final { scan-assembler {\sldp\tq12, q13} } } */
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/* { dg-final { scan-assembler {\sldp\tq14, q15} } } */
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/* { dg-final { scan-assembler {\sldp\tq16, q17} } } */
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/* { dg-final { scan-assembler {\sldp\tq18, q19} } } */
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/* { dg-final { scan-assembler {\sldp\tq20, q21} } } */
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/* { dg-final { scan-assembler {\sldp\tq22, q23} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\td} } } */
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/* { dg-final { scan-assembler-not {\sldp\td} } } */
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/* { dg-final { scan-assembler-not {\sstr\t} } } */
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/* { dg-final { scan-assembler-not {\sldr\t} } } */
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/* dg-do run */
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/* { dg-additional-options "-std=c99" } */
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/* There is nothing special about the calculations here, this is just
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a test that can be compiled and run. */
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extern void abort (void);
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__Float64x2_t __attribute__ ((noinline, aarch64_vector_pcs))
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foo(__Float64x2_t a, __Float64x2_t b, __Float64x2_t c,
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__Float64x2_t d, __Float64x2_t e, __Float64x2_t f,
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__Float64x2_t g, __Float64x2_t h, __Float64x2_t i)
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{
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__Float64x2_t w, x, y, z;
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w = a + b * c;
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x = d + e * f;
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y = g + h * i;
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return w + x * y;
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}
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int main()
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{
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__Float64x2_t a, b, c, d;
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a = (__Float64x2_t) { 1.0, 2.0 };
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b = (__Float64x2_t) { 3.0, 4.0 };
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c = (__Float64x2_t) { 5.0, 6.0 };
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d = foo (a, b, c, (a+b), (b+c), (a+c), (a-b), (b-c), (a-c)) + a + b + c;
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if (d[0] != 337.0 || d[1] != 554.0)
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abort ();
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return 0;
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}
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/* { dg-do compile } */
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void __attribute__ ((aarch64_vector_pcs))
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f (void)
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{
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/* Clobber some fp/simd regs and verify that only those are saved
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and restored in the prologue and epilogue of a SIMD function. */
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__asm__ __volatile__ ("" ::: "q8", "q9", "q10", "q11");
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}
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/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
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/* { dg-final { scan-assembler {\sstp\tq10, q11} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq1[23456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq1[23456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\td} } } */
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/* { dg-final { scan-assembler-not {\sldp\td} } } */
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/* { dg-final { scan-assembler-not {\sstr\t} } } */
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/* { dg-final { scan-assembler-not {\sldr\t} } } */
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/* { dg-do compile } */
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void __attribute__ ((aarch64_vector_pcs))
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f (void)
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{
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/* Clobber some fp/simd regs and verify that only those are saved
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and restored in the prologue and epilogue of a SIMD function. */
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__asm__ __volatile__ ("" ::: "q8", "q10", "q11");
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}
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/* { dg-final { scan-assembler {\sstp\tq8, q10} } } */
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/* { dg-final { scan-assembler {\sstr\tq11} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq[0345679]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq[0345679]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq1[123456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq1[123456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\td} } } */
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/* { dg-final { scan-assembler-not {\sldp\td} } } */
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/* { dg-final { scan-assembler-not {\sstr\tq[023456789]} } } */
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/* { dg-final { scan-assembler-not {\sldr\tq[023456789]} } } */
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/* { dg-final { scan-assembler-not {\sstr\tq1[023456789]} } } */
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/* { dg-final { scan-assembler-not {\sldr\tq1[023456789]} } } */
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/* { dg-do compile } */
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void __attribute__ ((aarch64_vector_pcs))
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f (void)
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{
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/* Clobber some fp/simd regs and verify that only those are saved
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and restored in the prologue and epilogue of a SIMD function. */
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__asm__ __volatile__ ("" ::: "q8", "q9", "q11");
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}
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/* { dg-final { scan-assembler {\sstp\tq8, q9} } } */
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/* { dg-final { scan-assembler {\sstr\tq11} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq[034567]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq1[0123456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq1[0123456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sldp\tq2[456789]} } } */
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/* { dg-final { scan-assembler-not {\sstp\td} } } */
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/* { dg-final { scan-assembler-not {\sldp\td} } } */
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/* { dg-final { scan-assembler-not {\sstr\tq[023456789]} } } */
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/* { dg-final { scan-assembler-not {\sldr\tq[023456789]} } } */
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/* { dg-final { scan-assembler-not {\sstr\tq1[023456789]} } } */
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/* { dg-final { scan-assembler-not {\sldr\tq1[023456789]} } } */
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