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neon.md (neon_vget_lanev2di): Use gen_lowpart and gen_highpart.
* neon.md (neon_vget_lanev2di): Use gen_lowpart and gen_highpart. * config/arm/neon.ml (Fixed_return_reg): Renamed to fixed_vector_reg. All callers changed. (Fixed_core_reg): New feature. (Vget_lane [sizes S64 and U64]): Add Fixed_core_reg. Allow fmrrd in disassembly. * neon-testgen.ml: Handle Fixed_core_reg. * gcc.target/arm/neon/vgetQ_laneu64.c: Regenerated. * gcc.target/arm/neon/vgetQ_lanes64.c: Likewise. From-SVN: r185603
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
216c92c984
commit
baeecefcd2
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@ -1,3 +1,13 @@
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2012-03-21 Richard Earnshaw <rearnsha@arm.com>
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* neon.md (neon_vget_lanev2di): Use gen_lowpart and gen_highpart.
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* config/arm/neon.ml (Fixed_return_reg): Renamed to fixed_vector_reg.
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All callers changed.
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(Fixed_core_reg): New feature.
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(Vget_lane [sizes S64 and U64]): Add Fixed_core_reg. Allow fmrrd in
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disassembly.
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* neon-testgen.ml: Handle Fixed_core_reg.
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2012-03-21 Andrew Stubbs <ams@codesourcery.com>
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* config/arm/arm.c (thumb2_reorg): Add complete support
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@ -79,9 +79,12 @@ let emit_automatics chan c_types features =
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(* The intrinsic returns a value. We need to do explict register
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allocation for vget_low tests or they fail because of copy
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elimination. *)
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((if List.mem Fixed_return_reg features then
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((if List.mem Fixed_vector_reg features then
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Printf.fprintf chan " register %s out_%s asm (\"d18\");\n"
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return_ty return_ty
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else if List.mem Fixed_core_reg features then
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Printf.fprintf chan " register %s out_%s asm (\"r0\");\n"
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return_ty return_ty
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else
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Printf.fprintf chan " %s out_%s;\n" return_ty return_ty);
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emit ())
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@ -2720,14 +2720,24 @@
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})
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(define_expand "neon_vget_lanev2di"
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[(match_operand:DI 0 "s_register_operand" "=r")
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(match_operand:V2DI 1 "s_register_operand" "w")
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(match_operand:SI 2 "immediate_operand" "i")
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(match_operand:SI 3 "immediate_operand" "i")]
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[(match_operand:DI 0 "s_register_operand" "")
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(match_operand:V2DI 1 "s_register_operand" "")
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(match_operand:SI 2 "immediate_operand" "")
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(match_operand:SI 3 "immediate_operand" "")]
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"TARGET_NEON"
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{
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neon_lane_bounds (operands[2], 0, 2);
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emit_insn (gen_vec_extractv2di (operands[0], operands[1], operands[2]));
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switch (INTVAL (operands[2]))
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{
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case 0:
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emit_move_insn (operands[0], gen_lowpart (DImode, operands[1]));
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break;
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case 1:
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emit_move_insn (operands[0], gen_highpart (DImode, operands[1]));
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break;
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default:
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neon_lane_bounds (operands[2], 0, 1);
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FAIL;
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}
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DONE;
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})
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@ -234,7 +234,8 @@ type features =
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cases. The function supplied must return the integer to be written
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into the testcase for the argument number (0-based) supplied to it. *)
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| Const_valuator of (int -> int)
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| Fixed_return_reg
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| Fixed_vector_reg
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| Fixed_core_reg
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exception MixedMode of elts * elts
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@ -1009,7 +1010,8 @@ let ops =
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Vget_lane,
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[InfoWord;
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Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
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Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
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Instruction_name ["vmov"; "fmrrd"]; Const_valuator (fun _ -> 0);
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Fixed_core_reg],
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Use_operands [| Corereg; Qreg; Immed |],
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"vgetQ_lane", notype_2, [S64; U64];
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@ -1125,7 +1127,7 @@ let ops =
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notype_1, pf_su_8_64;
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Vget_low, [Instruction_name ["vmov"];
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Disassembles_as [Use_operands [| Dreg; Dreg |]];
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Fixed_return_reg],
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Fixed_vector_reg],
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Use_operands [| Dreg; Qreg |], "vget_low",
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notype_1, pf_su_8_32;
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Vget_low, [No_op],
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@ -1,3 +1,8 @@
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2012-03-21 Richard Earnshaw <rearnsha@arm.com>
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* gcc.target/arm/neon/vgetQ_laneu64.c: Regenerated.
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* gcc.target/arm/neon/vgetQ_lanes64.c: Likewise.
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2012-03-21 Martin Jambor <mjambor@suse.cz>
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PR testsuite/52641
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@ -10,11 +10,11 @@
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void test_vgetQ_lanes64 (void)
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{
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int64_t out_int64_t;
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register int64_t out_int64_t asm ("r0");
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int64x2_t arg0_int64x2_t;
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out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
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}
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/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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@ -10,11 +10,11 @@
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void test_vgetQ_laneu64 (void)
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{
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uint64_t out_uint64_t;
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register uint64_t out_uint64_t asm ("r0");
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uint64x2_t arg0_uint64x2_t;
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out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
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}
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/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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