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re PR target/47246 (Invalid immediate offset for Thumb VFP store regression) 

2011-01-26  Chung-Lin Tang  <cltang@codesourcery.com>

	PR target/47246
	* config/arm/arm.c (thumb2_legitimate_index_p): Change the
	lower bound of the allowed Thumb-2 coprocessor load/store
	index range to -256. Add explaining comment.

From-SVN: r169271
This commit is contained in:
Chung-Lin Tang 2011-01-26 03:01:44 +00:00 committed by Chung-Lin Tang
parent 82c039077c
commit bff9926229
2 changed files with 12 additions and 1 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2011-01-26 Chung-Lin Tang <cltang@codesourcery.com>
PR target/47246
* config/arm/arm.c (thumb2_legitimate_index_p): Change the
lower bound of the allowed Thumb-2 coprocessor load/store
index range to -256. Add explaining comment.
2011-01-25 Ian Lance Taylor <iant@google.com> 2011-01-25 Ian Lance Taylor <iant@google.com>
* godump.c (go_define): Improve lexing of macro expansion to only * godump.c (go_define): Improve lexing of macro expansion to only

6
gcc/config/arm/arm.c
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@ -5786,7 +5786,11 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
&& (mode == SFmode || mode == DFmode && (mode == SFmode || mode == DFmode
|| (TARGET_MAVERICK && mode == DImode))) || (TARGET_MAVERICK && mode == DImode)))
return (code == CONST_INT && INTVAL (index) < 1024 return (code == CONST_INT && INTVAL (index) < 1024
&& INTVAL (index) > -1024 /* Thumb-2 allows only > -256 index range for it's core register
load/stores. Since we allow SF/DF in core registers, we have
to use the intersection between -256~4096 (core) and -1024~1024
(coprocessor). */
&& INTVAL (index) > -256
&& (INTVAL (index) & 3) == 0); && (INTVAL (index) & 3) == 0);
if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))