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re PR target/54212 (ARM: invalid instruction (vdupeq.32) generated) 

Fix PR target/54212

2012-08-15  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

	PR target/54212
	* config/arm/neon.md (vec_set<mode>_internal VD,VQ): Do not
	mark as predicable. Adjust asm template.
	(vec_setv2di_internal): Likewise.
	(vec_extract<mode> VD, VQ): Likewise.
	(vec_extractv2di): Likewise.
	(neon_vget_lane<mode>_sext_internal VD, VQ): Likewise.
	(neon_vset_lane<mode>_sext_internal VD, VQ): Likewise.
	(neon_vdup_n<mode> VX, V32): Likewise.
	(neon_vdup_nv2di): Likewise.

From-SVN: r190407
This commit is contained in:
Ramana Radhakrishnan 2012-08-15 07:56:41 +00:00 committed by Ramana Radhakrishnan
parent 73590b4f3a
commit c3b1709a71
2 changed files with 41 additions and 41 deletions
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13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
2012-08-15 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
PR target/54212
* config/arm/neon.md (vec_set<mode>_internal VD,VQ): Do not
mark as predicable. Adjust asm template.
(vec_setv2di_internal): Likewise.
(vec_extract<mode> VD, VQ): Likewise.
(vec_extractv2di): Likewise.
(neon_vget_lane<mode>_sext_internal VD, VQ): Likewise.
(neon_vset_lane<mode>_sext_internal VD, VQ): Likewise.
(neon_vdup_n<mode> VX, V32): Likewise.
(neon_vdup_nv2di): Likewise.
2012-08-14 Diego Novillo <dnovillo@google.com>
Merge from cxx-conversion branch. Configury.

69
gcc/config/arm/neon.md
View File

@ -434,10 +434,9 @@
elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
operands[2] = GEN_INT (elt);
return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
return "vmov.<V_sz_elem>\t%P0[%c2], %1";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_mcr")])
[(set_attr "neon_type" "neon_mcr")])
(define_insn "vec_set<mode>_internal"
[(set (match_operand:VQ 0 "s_register_operand" "=w")
@ -460,10 +459,9 @@
operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
operands[2] = GEN_INT (elt);
return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
return "vmov.<V_sz_elem>\t%P0[%c2], %1";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_mcr")]
[(set_attr "neon_type" "neon_mcr")]
)
(define_insn "vec_setv2di_internal"
@ -480,10 +478,9 @@
operands[0] = gen_rtx_REG (DImode, regno);
return "vmov%?\t%P0, %Q1, %R1";
return "vmov\t%P0, %Q1, %R1";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_mcr_2_mcrr")]
[(set_attr "neon_type" "neon_mcr_2_mcrr")]
)
(define_expand "vec_set<mode>"
@ -511,10 +508,9 @@
elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
operands[2] = GEN_INT (elt);
}
return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "vec_extract<mode>"
@ -535,10 +531,9 @@
operands[1] = gen_rtx_REG (<V_HALF>mode, regno + hi);
operands[2] = GEN_INT (elt);
return "vmov%?.<V_uf_sclr>\t%0, %P1[%c2]";
return "vmov.<V_uf_sclr>\t%0, %P1[%c2]";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "vec_extractv2di"
@ -552,10 +547,9 @@
operands[1] = gen_rtx_REG (DImode, regno);
return "vmov%?\t%Q0, %R0, %P1 @ v2di";
return "vmov\t%Q0, %R0, %P1 @ v2di";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_int_1")]
[(set_attr "neon_type" "neon_int_1")]
)
(define_expand "vec_init<mode>"
@ -2622,10 +2616,9 @@
elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
operands[2] = GEN_INT (elt);
}
return "vmov%?.s<V_sz_elem>\t%0, %P1[%c2]";
return "vmov.s<V_sz_elem>\t%0, %P1[%c2]";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lane<mode>_zext_internal"
@ -2642,10 +2635,9 @@
elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
operands[2] = GEN_INT (elt);
}
return "vmov%?.u<V_sz_elem>\t%0, %P1[%c2]";
return "vmov.u<V_sz_elem>\t%0, %P1[%c2]";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lane<mode>_sext_internal"
@ -2668,12 +2660,11 @@
ops[0] = operands[0];
ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
ops[2] = GEN_INT (elt_adj);
output_asm_insn ("vmov%?.s<V_sz_elem>\t%0, %P1[%c2]", ops);
output_asm_insn ("vmov.s<V_sz_elem>\t%0, %P1[%c2]", ops);
return "";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lane<mode>_zext_internal"
@ -2696,12 +2687,11 @@
ops[0] = operands[0];
ops[1] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
ops[2] = GEN_INT (elt_adj);
output_asm_insn ("vmov%?.u<V_sz_elem>\t%0, %P1[%c2]", ops);
output_asm_insn ("vmov.u<V_sz_elem>\t%0, %P1[%c2]", ops);
return "";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_expand "neon_vget_lane<mode>"
@ -2832,10 +2822,9 @@
[(set (match_operand:VX 0 "s_register_operand" "=w")
(vec_duplicate:VX (match_operand:<V_elem> 1 "s_register_operand" "r")))]
"TARGET_NEON"
"vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
"vdup.<V_sz_elem>\t%<V_reg>0, %1"
;; Assume this schedules like vmov.
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vdup_n<mode>"
@ -2843,11 +2832,10 @@
(vec_duplicate:V32 (match_operand:<V_elem> 1 "s_register_operand" "r,t")))]
"TARGET_NEON"
"@
vdup%?.<V_sz_elem>\t%<V_reg>0, %1
vdup%?.<V_sz_elem>\t%<V_reg>0, %y1"
vdup.<V_sz_elem>\t%<V_reg>0, %1
vdup.<V_sz_elem>\t%<V_reg>0, %y1"
;; Assume this schedules like vmov.
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_expand "neon_vdup_ndi"
@ -2865,10 +2853,9 @@
(vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))]
"TARGET_NEON"
"@
vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1
vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1"
[(set_attr "predicable" "yes")
(set_attr "length" "8")
vmov\t%e0, %Q1, %R1\;vmov\t%f0, %Q1, %R1
vmov\t%e0, %P1\;vmov\t%f0, %P1"
[(set_attr "length" "8")
(set_attr "neon_type" "neon_bp_simple")]
)