mirror of git://gcc.gnu.org/git/gcc.git
optabs.h: Change CTI_ to COI_.
2005-08-19 Eric Christopher <echristo@apple.com>
* optabs.h: Change CTI_ to COI_.
* optabs.c: Ditto.
From-SVN: r103295
This commit is contained in:
Eric Christopher
parent
c8f27794b8
commit
c414ac1d70
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@ -1,3 +1,8 @@
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2005-08-19 Eric Christopher <echristo@apple.com>
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* optabs.h: Change CTI_ to COI_.
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* optabs.c: Ditto.
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2005-08-19 James E Wilson <wilson@specifix.com>
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* builtins.c (expand_builtin_return_addr): Set
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@ -33,14 +38,14 @@
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block or not.
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(if_convertible_loop_p): Supply exit block itself to
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if_convertible_bb_p.
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2005-08-19 Richard Earnshaw <richard.earnshaw@arm.com>
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PR target/23473
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* arm.md (arm_load_pic_register): Change argument to the mask of
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saved registers. Call thumb_find_work_register if we need a
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saved registers. Call thumb_find_work_register if we need a
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scratch register on Thumb.
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(arm_expand_prologue): Pass empty register set to
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(arm_expand_prologue): Pass empty register set to
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arm_load_pic_register.
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(thumb_expand_prologue): Pass live_regs_mask directly to
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arm_load_pic_register.
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@ -151,7 +156,7 @@
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(plus_gtu<mode>): Same.
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2005-08-17 Erik Christiansen <erik@dd.nec.com.au>
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* config/v850/lib1funcs.asm (callt_save_interrupt): Fix comment typos.
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Move call_table_data to end. Delete spurious .text.
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(callt_save_all_interrupt): Fix comment typo.
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@ -188,8 +193,8 @@
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* config.gcc: Added z9-109 switch.
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* config/s390/2084.md ("x_int", "x_agen", "x_lr", "x_la", "x_larl",
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"x_load", "x_store", "x_branch", "x_call", "x_mul_hi", "x_mul_sidi",
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"x_div", "x_sem", "x_cs", "x_vs", "x_stm", "x_lm", "x_other",
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"x_fsimpdf", "x_fsimpsf", "x_fdivdf", "x_fdivsf", "x_floaddf",
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"x_div", "x_sem", "x_cs", "x_vs", "x_stm", "x_lm", "x_other",
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"x_fsimpdf", "x_fsimpsf", "x_fdivdf", "x_fdivsf", "x_floaddf",
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"x_floadsf", "x_fstore_df", "x_fstoresf", "x_ftoi", "x_itof"): Enable
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for "z9_109" cpu attribute.
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* config/s390/s390.c (z9_109_cost): New processor cost structure.
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@ -206,7 +211,7 @@
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(CONSTRAINT_LEN): Added length of O constraint.
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(CLZ_DEFINED_VALUE_AT_ZERO): Definition added.
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* config/s390/s390.md ("cpu"): New value z9_109 added.
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("*tstdi_extimm", "*tstdi_ccconly_extimm", "*tstsi_extimm",
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("*tstdi_extimm", "*tstdi_ccconly_extimm", "*tstsi_extimm",
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"*tstsi_cconly_extimm", "*movdi_64extimm", "*extendhidi2_extimm",
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"*extendqidi2_extimm", "*extendhisi2_extimm", "*extendqisi2_extimm",
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"*zero_extend<mode>si2_extimm", "*anddi3_extimm", "*iordi3_extimm",
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@ -220,7 +225,7 @@
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"*addsi3_carry1_cc", "*addsi3_carry2_cc", "*addsi3_cc", "addsi3",
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"*andsi3_cc", "*andsi3_cconly", "*andsi3_zarch", "*iorsi3_cc",
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"*iorsi3_cconly", "*iorsi3_zarch", "*xorsi3_cc", "*xorsi3_cconly",
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"*xorsi3", "*xorhi3", "*xorqi3"): Added instruction using extended
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"*xorsi3", "*xorhi3", "*xorqi3"): Added instruction using extended
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immediates.
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("extend<mode>di2", "extend<mode>si2", "zero_extend<mode>di2",
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"zero_extend<mode>si2"): Allow memory operands and don't manually emit
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@ -356,7 +361,7 @@
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2005-08-15 Richard Earnshaw <richard.earnshaw@arm.com>
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PR target/23355
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* arm.c (thumb_compute_save_reg_mask): Use similar logic to
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* arm.c (thumb_compute_save_reg_mask): Use similar logic to
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arm_compure_save_reg0_reg12_mask to determine when the PIC register
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must be saved.
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@ -389,7 +394,7 @@
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* aclocal.m4 (gcc_AC_FUNC_PRINTF_PTR): Delete.
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* configure.ac: Don't call gcc_AC_FUNC_PRINTF_PTR.
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* system.h (HOST_PTR_PRINTF): Don't define, poison it.
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* bitmap.c, c-decl.c, config/i386/i386-interix.h,
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config/iq2000/iq2000.c, mips-tfile.c, print-rtl.c, print-tree.c:
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Delete HOST_PTR_PRINTF.
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@ -424,7 +429,7 @@
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PR 23386
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* tree-data-ref.c (estimate_niter_from_size_of_data): When
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step is negative compute the estimation from init downwards to zero.
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2005-08-14 James A. Morrison <phython@gcc.gnu.org>
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* fold-const (fold_binary): Call fold_build2 instead of fold (build.
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@ -441,9 +446,9 @@
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2005-08-14 Daniel Berlin <dberlin@dberlin.org>
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Fix PR tree-optimization/22615
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* tree-ssa-structalias.c (solution_set_add): Handle
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first_vi_for_offset returning NULL.
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first_vi_for_offset returning NULL.
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(do_da_constraint): Ditto.
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(do_sd_constraint): Ditto.
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(do_ds_constraint): Ditto
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@ -451,7 +456,7 @@
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(build_constraint_graph): RHS is allowed be ANYTHING.
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(first_vi_for_offset): Return NULL if we couldn't find anything at
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the offset.
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2005-08-14 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390.c (s390_canonicalize_comparison): Prefer register
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@ -466,9 +471,9 @@
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2005-08-14 Ira Rosen <irar@il.ibm.com>
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PR tree-optimization/23320
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* tree-data-ref.c (base_addr_differ_p): Add comment. Check
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data-refs' types instead of base object nullness. Add check for
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pointer type data-refs before first location comparison. Remove
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* tree-data-ref.c (base_addr_differ_p): Add comment. Check
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data-refs' types instead of base object nullness. Add check for
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pointer type data-refs before first location comparison. Remove
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assert.
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2005-08-14 Andreas Schwab <schwab@suse.de>
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@ -508,7 +513,7 @@
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* tree-flow-inline.h (single_ssa_tree_operand, single_ssa_use_operand,
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single_ssa_def_operand, zero_ssa_operands): Fix documentation.
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* tree-flow.h (scev_probably_wraps_p): Declare with an extra parameter.
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* tree-scalar-evolution.c (instantiate_parameters_1): Factor entry
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* tree-scalar-evolution.c (instantiate_parameters_1): Factor entry
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condition.
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* tree-ssa-loop-ivcanon.c: Fix documentation.
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* tree-ssa-loop-ivopts.c (idx_find_step): Add a fixme note.
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@ -534,7 +539,7 @@
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2005-08-12 Gerald Pfeifer <gerald@pfeifer.com>
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* doc/invoke.texi (C++ Dialect Options): Add dynamic_cast to
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* doc/invoke.texi (C++ Dialect Options): Add dynamic_cast to
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description of -Wold-style-casts.
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2005-08-12 Andreas Krebbel <krebbel1@de.ibm.com>
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@ -589,7 +594,7 @@
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2005-08-12 Andreas Krebbel <krebbel1@de.ibm.com>
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* config/s390/s390.c (s390_split_branches, s390_init_frame_layout):
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* config/s390/s390.c (s390_split_branches, s390_init_frame_layout):
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Don't set save_return_addr_p.
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(s390_register_info): Make clobbered_regs not depending on
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save_return_addr_p.
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62
gcc/optabs.c
62
gcc/optabs.c
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@ -59,7 +59,7 @@ optab optab_table[OTI_MAX];
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rtx libfunc_table[LTI_MAX];
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/* Tables of patterns for converting one mode to another. */
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convert_optab convert_optab_table[CTI_MAX];
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convert_optab convert_optab_table[COI_MAX];
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/* Contains the optab used for each rtx code. */
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optab code_to_optab[NUM_RTX_CODE + 1];
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@ -349,8 +349,8 @@ optab_for_tree_code (enum tree_code code, tree type)
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this may or may not be TARGET. */
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rtx
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expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0,
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rtx op1, rtx op2, rtx target, int unsignedp)
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expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0,
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rtx op1, rtx op2, rtx target, int unsignedp)
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{
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int icode = (int) ternary_optab->handlers[(int) mode].insn_code;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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@ -377,7 +377,7 @@ expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0,
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if (GET_MODE (op0) != mode0 && mode0 != VOIDmode)
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xop0 = convert_modes (mode0,
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GET_MODE (op0) != VOIDmode
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? GET_MODE (op0)
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? GET_MODE (op0)
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: mode,
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xop0, unsignedp);
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@ -397,23 +397,23 @@ expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0,
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/* Now, if insn's predicates don't allow our operands, put them into
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pseudo regs. */
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if (!insn_data[icode].operand[1].predicate (xop0, mode0)
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&& mode0 != VOIDmode)
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&& mode0 != VOIDmode)
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xop0 = copy_to_mode_reg (mode0, xop0);
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if (!insn_data[icode].operand[2].predicate (xop1, mode1)
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&& mode1 != VOIDmode)
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xop1 = copy_to_mode_reg (mode1, xop1);
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if (!insn_data[icode].operand[3].predicate (xop2, mode2)
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&& mode2 != VOIDmode)
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xop2 = copy_to_mode_reg (mode2, xop2);
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pat = GEN_FCN (icode) (temp, xop0, xop1, xop2);
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emit_insn (pat);
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return temp;
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return temp;
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}
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@ -2192,7 +2192,7 @@ expand_parity (enum machine_mode mode, rtx op0, rtx target)
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return 0;
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}
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/* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
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/* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
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conditions, VAL may already be a SUBREG against which we cannot generate
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a further SUBREG. In this case, we expect forcing the value into a
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register will work around the situation. */
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@ -2282,7 +2282,7 @@ expand_absneg_bit (enum rtx_code code, enum machine_mode mode,
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{
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rtx targ_piece = operand_subword (target, i, 1, mode);
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rtx op0_piece = operand_subword_force (op0, i, mode);
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if (i == word)
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{
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temp = expand_binop (imode, code == ABS ? and_optab : xor_optab,
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@ -2854,7 +2854,7 @@ expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target,
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{
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rtx targ_piece = operand_subword (target, i, 1, mode);
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rtx op0_piece = operand_subword_force (op0, i, mode);
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if (i == word)
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{
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if (!op0_is_abs)
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@ -2901,7 +2901,7 @@ expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target,
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return target;
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}
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/* Expand the C99 copysign operation. OP0 and OP1 must be the same
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/* Expand the C99 copysign operation. OP0 and OP1 must be the same
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scalar floating point mode. Return NULL if we do not know how to
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expand the operation inline. */
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@ -5282,7 +5282,7 @@ debug_optab_libfuncs (void)
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}
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/* Dump the conversion optabs. */
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for (i = 0; i < (int) CTI_MAX; ++i)
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for (i = 0; i < (int) COI_MAX; ++i)
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for (j = 0; j < NUM_MACHINE_MODES; ++j)
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for (k = 0; k < NUM_MACHINE_MODES; ++k)
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{
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@ -5377,7 +5377,7 @@ get_rtx_code (enum tree_code tcode, bool unsignedp)
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case GE_EXPR:
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code = unsignedp ? GEU : GE;
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break;
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case UNORDERED_EXPR:
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code = UNORDERED;
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break;
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@ -5423,10 +5423,10 @@ vector_compare_rtx (tree cond, bool unsignedp, enum insn_code icode)
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ensures that condition is a relational operation. */
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gcc_assert (COMPARISON_CLASS_P (cond));
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rcode = get_rtx_code (TREE_CODE (cond), unsignedp);
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rcode = get_rtx_code (TREE_CODE (cond), unsignedp);
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t_op0 = TREE_OPERAND (cond, 0);
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t_op1 = TREE_OPERAND (cond, 1);
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/* Expand operands. */
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rtx_op0 = expand_expr (t_op0, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op0)), 1);
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rtx_op1 = expand_expr (t_op1, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op1)), 1);
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@ -5434,7 +5434,7 @@ vector_compare_rtx (tree cond, bool unsignedp, enum insn_code icode)
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if (!insn_data[icode].operand[4].predicate (rtx_op0, GET_MODE (rtx_op0))
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&& GET_MODE (rtx_op0) != VOIDmode)
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rtx_op0 = force_reg (GET_MODE (rtx_op0), rtx_op0);
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if (!insn_data[icode].operand[5].predicate (rtx_op1, GET_MODE (rtx_op1))
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&& GET_MODE (rtx_op1) != VOIDmode)
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rtx_op1 = force_reg (GET_MODE (rtx_op1), rtx_op1);
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@ -5443,8 +5443,8 @@ vector_compare_rtx (tree cond, bool unsignedp, enum insn_code icode)
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}
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/* Return insn code for VEC_COND_EXPR EXPR. */
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static inline enum insn_code
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static inline enum insn_code
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get_vcond_icode (tree expr, enum machine_mode mode)
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{
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enum insn_code icode = CODE_FOR_nothing;
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@ -5485,7 +5485,7 @@ expand_vec_cond_expr (tree vec_cond_expr, rtx target)
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target = gen_reg_rtx (mode);
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/* Get comparison rtx. First expand both cond expr operands. */
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comparison = vector_compare_rtx (TREE_OPERAND (vec_cond_expr, 0),
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comparison = vector_compare_rtx (TREE_OPERAND (vec_cond_expr, 0),
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unsignedp, icode);
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cc_op0 = XEXP (comparison, 0);
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cc_op1 = XEXP (comparison, 1);
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|
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@ -5503,7 +5503,7 @@ expand_vec_cond_expr (tree vec_cond_expr, rtx target)
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rtx_op2 = force_reg (mode, rtx_op2);
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/* Emit instruction! */
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emit_insn (GEN_FCN (icode) (target, rtx_op1, rtx_op2,
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emit_insn (GEN_FCN (icode) (target, rtx_op1, rtx_op2,
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comparison, cc_op0, cc_op1));
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return target;
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|
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@ -5629,8 +5629,8 @@ expand_bool_compare_and_swap (rtx mem, rtx old_val, rtx new_val, rtx target)
|
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}
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}
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|
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/* Without an appropriate setcc instruction, use a set of branches to
|
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get 1 and 0 stored into target. Presumably if the target has a
|
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/* Without an appropriate setcc instruction, use a set of branches to
|
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get 1 and 0 stored into target. Presumably if the target has a
|
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STORE_FLAG_VALUE that isn't 1, then this will get cleaned up by ifcvt. */
|
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|
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label0 = gen_label_rtx ();
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|
|
@ -5723,7 +5723,7 @@ expand_compare_and_swap_loop (rtx mem, rtx old_reg, rtx new_reg, rtx seq)
|
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}
|
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|
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/* This function generates the atomic operation MEM CODE= VAL. In this
|
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case, we do not care about any resulting value. Returns NULL if we
|
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case, we do not care about any resulting value. Returns NULL if we
|
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cannot generate the operation. */
|
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|
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rtx
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|
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@ -5776,7 +5776,7 @@ expand_sync_operation (rtx mem, rtx val, enum rtx_code code)
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val = convert_modes (mode, GET_MODE (val), val, 1);
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if (!insn_data[icode].operand[1].predicate (val, mode))
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val = force_reg (mode, val);
|
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|
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|
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insn = GEN_FCN (icode) (mem, val);
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if (insn)
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{
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|
|
@ -5814,7 +5814,7 @@ expand_sync_operation (rtx mem, rtx val, enum rtx_code code)
|
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|
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/* This function generates the atomic operation MEM CODE= VAL. In this
|
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case, we do care about the resulting value: if AFTER is true then
|
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return the value MEM holds after the operation, if AFTER is false
|
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return the value MEM holds after the operation, if AFTER is false
|
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then return the value MEM holds before the operation. TARGET is an
|
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optional place for the result value to be stored. */
|
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|
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|
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@ -5909,7 +5909,7 @@ expand_sync_fetch_operation (rtx mem, rtx val, enum rtx_code code,
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val = convert_modes (mode, GET_MODE (val), val, 1);
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if (!insn_data[icode].operand[2].predicate (val, mode))
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val = force_reg (mode, val);
|
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|
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|
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insn = GEN_FCN (icode) (target, mem, val);
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if (insn)
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{
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||||
|
|
@ -5974,7 +5974,7 @@ expand_sync_fetch_operation (rtx mem, rtx val, enum rtx_code code,
|
|||
/* This function expands a test-and-set operation. Ideally we atomically
|
||||
store VAL in MEM and return the previous value in MEM. Some targets
|
||||
may not support this operation and only support VAL with the constant 1;
|
||||
in this case while the return value will be 0/1, but the exact value
|
||||
in this case while the return value will be 0/1, but the exact value
|
||||
stored in MEM is target defined. TARGET is an option place to stick
|
||||
the return value. */
|
||||
|
||||
|
|
|
|||
44
gcc/optabs.h
44
gcc/optabs.h
|
|
@ -377,33 +377,33 @@ extern GTY(()) optab optab_table[OTI_MAX];
|
|||
/* Conversion optabs have their own table and indexes. */
|
||||
enum convert_optab_index
|
||||
{
|
||||
CTI_sext,
|
||||
CTI_zext,
|
||||
CTI_trunc,
|
||||
COI_sext,
|
||||
COI_zext,
|
||||
COI_trunc,
|
||||
|
||||
CTI_sfix,
|
||||
CTI_ufix,
|
||||
COI_sfix,
|
||||
COI_ufix,
|
||||
|
||||
CTI_sfixtrunc,
|
||||
CTI_ufixtrunc,
|
||||
COI_sfixtrunc,
|
||||
COI_ufixtrunc,
|
||||
|
||||
CTI_sfloat,
|
||||
CTI_ufloat,
|
||||
COI_sfloat,
|
||||
COI_ufloat,
|
||||
|
||||
CTI_MAX
|
||||
COI_MAX
|
||||
};
|
||||
|
||||
extern GTY(()) convert_optab convert_optab_table[CTI_MAX];
|
||||
extern GTY(()) convert_optab convert_optab_table[COI_MAX];
|
||||
|
||||
#define sext_optab (convert_optab_table[CTI_sext])
|
||||
#define zext_optab (convert_optab_table[CTI_zext])
|
||||
#define trunc_optab (convert_optab_table[CTI_trunc])
|
||||
#define sfix_optab (convert_optab_table[CTI_sfix])
|
||||
#define ufix_optab (convert_optab_table[CTI_ufix])
|
||||
#define sfixtrunc_optab (convert_optab_table[CTI_sfixtrunc])
|
||||
#define ufixtrunc_optab (convert_optab_table[CTI_ufixtrunc])
|
||||
#define sfloat_optab (convert_optab_table[CTI_sfloat])
|
||||
#define ufloat_optab (convert_optab_table[CTI_ufloat])
|
||||
#define sext_optab (convert_optab_table[COI_sext])
|
||||
#define zext_optab (convert_optab_table[COI_zext])
|
||||
#define trunc_optab (convert_optab_table[COI_trunc])
|
||||
#define sfix_optab (convert_optab_table[COI_sfix])
|
||||
#define ufix_optab (convert_optab_table[COI_ufix])
|
||||
#define sfixtrunc_optab (convert_optab_table[COI_sfixtrunc])
|
||||
#define ufixtrunc_optab (convert_optab_table[COI_ufixtrunc])
|
||||
#define sfloat_optab (convert_optab_table[COI_sfloat])
|
||||
#define ufloat_optab (convert_optab_table[COI_ufloat])
|
||||
|
||||
/* These arrays record the insn_code of insns that may be needed to
|
||||
perform input and output reloads of special objects. They provide a
|
||||
|
|
@ -492,8 +492,8 @@ extern enum insn_code sync_lock_release[NUM_MACHINE_MODES];
|
|||
|
||||
/* Define functions given in optabs.c. */
|
||||
|
||||
extern rtx expand_ternary_op (enum machine_mode mode, optab ternary_optab,
|
||||
rtx op0, rtx op1, rtx op2, rtx target,
|
||||
extern rtx expand_ternary_op (enum machine_mode mode, optab ternary_optab,
|
||||
rtx op0, rtx op1, rtx op2, rtx target,
|
||||
int unsignedp);
|
||||
|
||||
/* Expand a binary operation given optab and rtx operands. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue