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aarch64: Sync aarch64-sys-regs.def with Binutils 

This patch incorporates changes to this file in Binutils since March
2024 (excluding one patch that was already cherry-picked by
Ezra in July 2025).  It includes:
- New system registers in the 2024 and 2025 architecture extensions.
- Updated feature requirements for most system register accessors.
- Removal of registers that were dropped from the architecture.
- Removal of the unnecessary F_ARCHEXT flag.
- Fixed encoding for pmsdsfr_el1.

The updated architecture feature requirements are only relevant when the
new `-menable-sysreg-checking' option is enabled.

gcc/ChangeLog:

	* config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
	* config/aarch64/aarch64.cc (F_ARCHEXT): Delete flag.
	* config/aarch64/aarch64.h
	(AARCH64_FL_AMU): Delete unused macro.
	(AARCH64_FL_SCXTNUM): Ditto.
	(AARCH64_FL_ID_PFR2): Ditto.
	(AARCH64_FL_AIE): Ditto.
	(AARCH64_FL_DEBUGv8p9): Ditto.
	(AARCH64_FL_FGT2): Ditto.
	(AARCH64_FL_PFAR): Ditto.
	(AARCH64_FL_PMUv3_ICNTR): Ditto.
	(AARCH64_FL_PMUv3_SS): Ditto.
	(AARCH64_FL_PMUv3p9): Ditto.
	(AARCH64_FL_S1PIE): Ditto.
	(AARCH64_FL_S1POE): Ditto.
	(AARCH64_FL_S2PIE): Ditto.
	(AARCH64_FL_S2POE): Ditto.
	(AARCH64_FL_SCTLR2): Ditto.
	(AARCH64_FL_SEBEP): Ditto.
	(AARCH64_FL_SPE_FDS): Ditto.
	(AARCH64_FL_TCR2): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/acle/rwsr-armv8p9.c: Fix incorrect encoding.
This commit is contained in:
Alice Carlotti 2025-10-13 17:52:02 +01:00
parent f708b83d19
commit c62f3e81a0
4 changed files with 1256 additions and 1152 deletions
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2375
gcc/config/aarch64/aarch64-sys-regs.def
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File diff suppressed because it is too large Load Diff

1
gcc/config/aarch64/aarch64.cc
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@ -519,7 +519,6 @@ typedef struct {
#define F_DEPRECATED (1 << 1)
#define F_REG_READ (1 << 2)
#define F_REG_WRITE (1 << 3)
#define F_ARCHEXT (1 << 4)
/* Flag indicating register name is alias for another system register. */
#define F_REG_ALIAS (1 << 5)
/* Flag indicatinig registers which may be implemented with 128-bits. */

30
gcc/config/aarch64/aarch64.h
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@ -240,44 +240,22 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
#define TARGET_SIMD (TARGET_BASE_SIMD && TARGET_NON_STREAMING)
#define TARGET_FLOAT AARCH64_HAVE_ISA (FP)
/* AARCH64_FL options necessary for system register implementation. */
/* Define AARCH64_FL aliases for architectural features which are protected
by -march flags in binutils but which receive no special treatment by GCC.
These features are used in the aarch64-sys-regs.def file, which is copied
from Binutils.
Such flags are inherited from the Binutils definition of system registers
and are mapped to the architecture in which the feature is implemented. */
We should try to eliminate these inconsistencies in future. */
#define AARCH64_FL_RAS AARCH64_FL_V8A
#define AARCH64_FL_LOR AARCH64_FL_V8_1A
#define AARCH64_FL_PAN AARCH64_FL_V8_1A
#define AARCH64_FL_AMU AARCH64_FL_V8_4A
#define AARCH64_FL_SCXTNUM AARCH64_FL_V8_5A
#define AARCH64_FL_ID_PFR2 AARCH64_FL_V8_5A
/* Armv8.9-A extension feature bits defined in Binutils but absent from GCC,
aliased to their base architecture. */
#define AARCH64_FL_AIE AARCH64_FL_V8_9A
#define AARCH64_FL_DEBUGv8p9 AARCH64_FL_V8_9A
#define AARCH64_FL_FGT2 AARCH64_FL_V8_9A
#define AARCH64_FL_ITE AARCH64_FL_V8_9A
#define AARCH64_FL_PFAR AARCH64_FL_V8_9A
#define AARCH64_FL_PMUv3_ICNTR AARCH64_FL_V8_9A
#define AARCH64_FL_PMUv3_SS AARCH64_FL_V8_9A
#define AARCH64_FL_PMUv3p9 AARCH64_FL_V8_9A
#define AARCH64_FL_RASv2 AARCH64_FL_V8_9A
#define AARCH64_FL_S1PIE AARCH64_FL_V8_9A
#define AARCH64_FL_S1POE AARCH64_FL_V8_9A
#define AARCH64_FL_S2PIE AARCH64_FL_V8_9A
#define AARCH64_FL_S2POE AARCH64_FL_V8_9A
#define AARCH64_FL_SCTLR2 AARCH64_FL_V8_9A
#define AARCH64_FL_SEBEP AARCH64_FL_V8_9A
#define AARCH64_FL_SPE_FDS AARCH64_FL_V8_9A
#define AARCH64_FL_TCR2 AARCH64_FL_V8_9A
#define TARGET_V8R AARCH64_HAVE_ISA (V8R)
#define TARGET_V9A AARCH64_HAVE_ISA (V9A)
/* SHA2 is an optional extension to AdvSIMD. */
#define TARGET_SHA2 AARCH64_HAVE_ISA (SHA2)

2
gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
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@ -72,7 +72,7 @@ readwrite_armv8p9a_sysregs (long long int a)
a = __arm_rsr64 ("pmicfiltr_el0"); /* { { dg-final { scan-assembler "mrs\tx0, s3_3_c9_c6_0" } } */
a = __arm_rsr64 ("pmicntr_el0"); /* { { dg-final { scan-assembler "mrs\tx0, s3_3_c9_c4_0" } } */
a = __arm_rsr64 ("pmicntsvr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s2_0_c14_c12_0" } } */
a = __arm_rsr64 ("pmsdsfr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_4_c9_c10_4" } } */
a = __arm_rsr64 ("pmsdsfr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_0_c9_c10_4" } } */
a = __arm_rsr64 ("pmsscr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_0_c9_c13_3" } } */
a = __arm_rsr64 ("pmuacr_el1"); /* { { dg-final { scan-assembler "mrs\tx0, s3_0_c9_c14_4" } } */
a = __arm_rsr64 ("por_el0"); /* { { dg-final { scan-assembler "mrs\tx0, s3_3_c10_c2_4" } } */