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arm.c (arm_emit_coreregs_64bit_shift): Clear the result register only if "in" and "out" are different registers. 

2016-10-19  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        * config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result
        register only if "in" and "out" are different registers.

From-SVN: r241348
This commit is contained in:
Bernd Edlinger 2016-10-19 17:02:30 +00:00 committed by Bernd Edlinger
parent 29849c91e4
commit c6cc81d613
2 changed files with 13 additions and 3 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2016-10-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result
register only if "in" and "out" are different registers.
2016-10-19 Eric Botcazou <ebotcazou@adacore.com> 2016-10-19 Eric Botcazou <ebotcazou@adacore.com>
* omp-low.c (pass_oacc_device_lower::gate): New method. * omp-low.c (pass_oacc_device_lower::gate): New method.

11
gcc/config/arm/arm.c
View File

@ -29218,8 +29218,10 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
/* Clearing the out register in DImode first avoids lots /* Clearing the out register in DImode first avoids lots
of spilling and results in less stack usage. of spilling and results in less stack usage.
Later this redundant insn is completely removed. */ Later this redundant insn is completely removed.
emit_insn (SET (out, const0_rtx)); Do that only if "in" and "out" are different registers. */
if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in))
emit_insn (SET (out, const0_rtx));
emit_insn (SET (out_down, LSHIFT (code, in_down, amount))); emit_insn (SET (out_down, LSHIFT (code, in_down, amount)));
emit_insn (SET (out_down, emit_insn (SET (out_down,
ORR (REV_LSHIFT (code, in_up, reverse_amount), ORR (REV_LSHIFT (code, in_up, reverse_amount),
@ -29231,11 +29233,14 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
/* Shifts by a constant greater than 31. */ /* Shifts by a constant greater than 31. */
rtx adj_amount = GEN_INT (INTVAL (amount) - 32); rtx adj_amount = GEN_INT (INTVAL (amount) - 32);
emit_insn (SET (out, const0_rtx)); if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in))
emit_insn (SET (out, const0_rtx));
emit_insn (SET (out_down, SHIFT (code, in_up, adj_amount))); emit_insn (SET (out_down, SHIFT (code, in_up, adj_amount)));
if (code == ASHIFTRT) if (code == ASHIFTRT)
emit_insn (gen_ashrsi3 (out_up, in_up, emit_insn (gen_ashrsi3 (out_up, in_up,
GEN_INT (31))); GEN_INT (31)));
else
emit_insn (SET (out_up, const0_rtx));
} }
} }
else else