mirror of git://gcc.gnu.org/git/gcc.git
i386.md (sqrt_extend<mode>xf3_i387): Remove.
* config/i386/i386.md (sqrt_extend<mode>xf3_i387): Remove. (sqrt<mode>2): Extend operand 1 to XFmode and generate sqrtxf3 insn. From-SVN: r264243
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@ -1,3 +1,8 @@
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2018-09-12 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (sqrt_extend<mode>xf3_i387): Remove.
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(sqrt<mode>2): Extend operand 1 to XFmode and generate sqrtxf3 insn.
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2018-09-12 Richard Biener <rguenther@suse.de>
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2018-09-12 Richard Biener <rguenther@suse.de>
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PR tree-optimization/87280
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PR tree-optimization/87280
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@ -15126,19 +15126,6 @@
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(set_attr "amdfam10_decode" "direct")
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(set_attr "amdfam10_decode" "direct")
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(set_attr "bdver1_decode" "direct")])
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(set_attr "bdver1_decode" "direct")])
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(define_insn "sqrt_extend<mode>xf2_i387"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(sqrt:XF
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(float_extend:XF
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(match_operand:MODEF 1 "register_operand" "0"))))]
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"TARGET_USE_FANCY_MATH_387"
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"fsqrt"
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[(set_attr "type" "fpspc")
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(set_attr "mode" "XF")
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(set_attr "athlon_decode" "direct")
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(set_attr "amdfam10_decode" "direct")
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(set_attr "bdver1_decode" "direct")])
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(define_insn "*rsqrtsf2_sse"
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(define_insn "*rsqrtsf2_sse"
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[(set (match_operand:SF 0 "register_operand" "=x,x")
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[(set (match_operand:SF 0 "register_operand" "=x,x")
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(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
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(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
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@ -15201,9 +15188,10 @@
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if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
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if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
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{
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{
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op1 = force_reg (<MODE>mode, operands[1]);
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rtx op1 = gen_reg_rtx (XFmode);
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emit_insn (gen_sqrt_extend<mode>xf2_i387 (op0, op1));
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emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
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emit_insn (gen_sqrtxf2 (op0, op1));
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emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
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emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
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DONE;
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DONE;
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}
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}
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