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re PR target/78310 (ICE: insn does not satisfy its constraints: {*bmi2_rorxdi3_1} with -mbmi2) 

PR target/78310
	* config/i386/i386.md (rotate to rotatex splitter): Avoid overflow
	when calculating operand 2.
	(rotate to rotatex zext splitter): Ditto.

testsuite/ChangeLog:

	PR target/78310
	* gcc.target/i386/pr78310.c: New test.

From-SVN: r242076
This commit is contained in:
Uros Bizjak 2016-11-11 17:21:52 +01:00
parent 606f928d38
commit c901bc0d8e
4 changed files with 41 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
gcc/ChangeLog
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@ -1,3 +1,10 @@
2016-11-11 Uros Bizjak <ubizjak@gmail.com>
PR target/78310
* config/i386/i386.md (rotate to rotatex splitter): Avoid overflow
when calculating operand 2.
(rotate to rotatex zext splitter): Ditto.
2016-11-11 Jeff Law <law@redhat.com> 2016-11-11 Jeff Law <law@redhat.com>
* gimple-ssa-isolate-paths.c (is_divmod_with_given_divisor): New * gimple-ssa-isolate-paths.c (is_divmod_with_given_divisor): New
@ -43,10 +50,8 @@
(rs6000_secondary_reload_simple_move): Likewise. (rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Don't force integer constants to (rs6000_preferred_reload_class): Don't force integer constants to
be loaded into vector registers that we can easily make into be loaded into vector registers that we can easily make into
memory (or being created in the GPRs and moved over with direct memory (or being created in the GPRs and moved over with direct move).
move). * config/rs6000/vsx.md (UNSPEC_P9_MEMORY): Delete, no longer used.
* config/rs6000/vsx.md (UNSPEC_P9_MEMORY): Delete, no longer
used.
(vsx_extract_<mode>): Rework V4SImode, V8HImode, and V16QImode (vsx_extract_<mode>): Rework V4SImode, V8HImode, and V16QImode
vector extraction on ISA 3.0 when the scalar integer can be vector extraction on ISA 3.0 when the scalar integer can be
allocated in vector registers. Generate the VEC_SELECT directy, allocated in vector registers. Generate the VEC_SELECT directy,
@ -70,8 +75,7 @@
(zero_extendhi<mode>): Likewise. (zero_extendhi<mode>): Likewise.
(extendqi<mode>): Likewise. (extendqi<mode>): Likewise.
(extendhi<mode>2): Likewise. (extendhi<mode>2): Likewise.
(HImode splitter for load/sign extend in vector register): (HImode splitter for load/sign extend in vector register): Likewise.
Likewise.
(float<QHI:mode><FP_ISA3:mode>2): Eliminate old method of (float<QHI:mode><FP_ISA3:mode>2): Eliminate old method of
optimizing floating point conversions to/from small data types and optimizing floating point conversions to/from small data types and
rewrite it to support QImode/HImode being allowed in vector rewrite it to support QImode/HImode being allowed in vector
@ -98,8 +102,8 @@
2016-11-10 Pat Haugen <pthaugen@us.ibm.com> 2016-11-10 Pat Haugen <pthaugen@us.ibm.com>
PR rtl-optimization/78241 PR rtl-optimization/78241
* loop-unroll.c (unroll_loop_runtime_iterations): Don't adjust 'niter', but * loop-unroll.c (unroll_loop_runtime_iterations): Don't adjust 'niter',
emit initial peel copy if niter expr is not reliable. but emit initial peel copy if niter expr is not reliable.
2016-11-10 Segher Boessenkool <segher@kernel.crashing.org> 2016-11-10 Segher Boessenkool <segher@kernel.crashing.org>
@ -180,8 +184,7 @@
2016-11-10 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org> 2016-11-10 Siddhesh Poyarekar <siddhesh.poyarekar@linaro.org>
* config/aarch64/aarch64-cores.def (qdf24xx): Update part * config/aarch64/aarch64-cores.def (qdf24xx): Update part number.
number.
(falkor): New core. (falkor): New core.
* config/aarch64/aarch64-tune.md: Regenerated. * config/aarch64/aarch64-tune.md: Regenerated.
* config/arm/arm-cores.def (falkor): New core. * config/arm/arm-cores.def (falkor): New core.

10
gcc/config/i386/i386.md
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@ -10908,8 +10908,9 @@
[(set (match_dup 0) [(set (match_dup 0)
(rotatert:SWI48 (match_dup 1) (match_dup 2)))] (rotatert:SWI48 (match_dup 1) (match_dup 2)))]
{ {
operands[2] int bitsize = GET_MODE_BITSIZE (<MODE>mode);
= GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
operands[2] = GEN_INT ((bitsize - INTVAL (operands[2])) % bitsize);
}) })
(define_split (define_split
@ -10975,8 +10976,9 @@
[(set (match_dup 0) [(set (match_dup 0)
(zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))] (zero_extend:DI (rotatert:SI (match_dup 1) (match_dup 2))))]
{ {
operands[2] int bitsize = GET_MODE_BITSIZE (SImode);
= GEN_INT (GET_MODE_BITSIZE (SImode) - INTVAL (operands[2]));
operands[2] = GEN_INT ((bitsize - INTVAL (operands[2])) % bitsize);
}) })
(define_split (define_split

9
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2016-11-11 Uros Bizjak <ubizjak@gmail.com>
PR target/78310
* gcc.target/i386/pr78310.c: New test.
2016-11-11 Jeff Law <law@redhat.com> 2016-11-11 Jeff Law <law@redhat.com>
* gcc.dg/tree-ssa/isolate-6.c: New test. * gcc.dg/tree-ssa/isolate-6.c: New test.
@ -2892,8 +2897,8 @@
arm_fp16_alternative_ok. arm_fp16_alternative_ok.
* g++.dg/ext/arm-fp16/arm-fp16-ops-4.C: Likewise. * g++.dg/ext/arm-fp16/arm-fp16-ops-4.C: Likewise.
* gcc.dg/torture/arm-fp16-int-convert-alt.c: Likewise. * gcc.dg/torture/arm-fp16-int-convert-alt.c: Likewise.
* gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c: Likewise. * gcc.dg/torture/arm-fp16-ops-3.c: Likewise.
* gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c: Likewise. * gcc.dg/torture/arm-fp16-ops-4.c: Likewise.
* gcc.target/arm/fp16-compile-alt-1.c: Likewise. * gcc.target/arm/fp16-compile-alt-1.c: Likewise.
* gcc.target/arm/fp16-compile-alt-10.c: Likewise. * gcc.target/arm/fp16-compile-alt-10.c: Likewise.
* gcc.target/arm/fp16-compile-alt-11.c: Likewise. * gcc.target/arm/fp16-compile-alt-11.c: Likewise.

15
gcc/testsuite/gcc.target/i386/pr78310.c Normal file
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@ -0,0 +1,15 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O -mbmi2" } */
unsigned long long a;
int b;
int
fn1(int p1)
{
p1 &= 1;
p1 &= (short)~p1;
b = a;
a = a << p1 | a >> (64 - p1);
return p1 + 1 + a;
}