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re PR target/62120 ([ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be disable in 32-bit) 

Fix PR 62120.

gcc/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * varasm.c (decode_reg_name_and_count): Check availability for
       registers from ADDITIONAL_REGISTER_NAMES.

testsuite/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * gcc.target/i386/avx512f-additional-reg-names.c: Use register valid
       in 32-bit mode.
       * gcc.target/i386/pr62120.c: New.

From-SVN: r215729
This commit is contained in:
Ilya Tocar 2014-09-30 16:04:15 +00:00 committed by Ilya Tocar
parent b355f52ed1
commit cd91371c5f
5 changed files with 25 additions and 3 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2014-09-30 Ilya Tocar <ilya.tocar@intel.com>
PR middle-end/62120
* varasm.c (decode_reg_name_and_count): Check availability for
registers from ADDITIONAL_REGISTER_NAMES.
2014-09-30 David Malcolm <dmalcolm@redhat.com> 2014-09-30 David Malcolm <dmalcolm@redhat.com>
PR plugins/63410 PR plugins/63410

7
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2014-09-30 Ilya Tocar <ilya.tocar@intel.com>
PR middle-end/62120
* gcc.target/i386/avx512f-additional-reg-names.c: Use register valid
in 32-bit mode.
* gcc.target/i386/pr62120.c: New.
2014-09-30 James Greenhalgh <james.greenhalgh@arm.com> 2014-09-30 James Greenhalgh <james.greenhalgh@arm.com>
* gcc.target/aarch64/simd/vqdmullh_laneq_s16.c: New. * gcc.target/aarch64/simd/vqdmullh_laneq_s16.c: New.

2
gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
View File

@ -3,7 +3,7 @@
void foo () void foo ()
{ {
register int zmm_var asm ("zmm9") __attribute__((unused)); register int zmm_var asm ("zmm6") __attribute__((unused));
__asm__ __volatile__("vxorpd %%zmm0, %%zmm0, %%zmm7\n" : : : "zmm7" ); __asm__ __volatile__("vxorpd %%zmm0, %%zmm0, %%zmm7\n" : : : "zmm7" );
} }

8
gcc/testsuite/gcc.target/i386/pr62120.c Normal file
View File

@ -0,0 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-mno-sse" } */
void foo ()
{
register int zmm_var asm ("ymm9");/* { dg-error "invalid register name" } */
register int zmm_var2 asm ("23");/* { dg-error "invalid register name" } */
}

5
gcc/varasm.c
View File

@ -888,7 +888,7 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs)
if (asmspec[0] != 0 && i < 0) if (asmspec[0] != 0 && i < 0)
{ {
i = atoi (asmspec); i = atoi (asmspec);
if (i < FIRST_PSEUDO_REGISTER && i >= 0) if (i < FIRST_PSEUDO_REGISTER && i >= 0 && reg_names[i][0])
return i; return i;
else else
return -2; return -2;
@ -925,7 +925,8 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs)
for (i = 0; i < (int) ARRAY_SIZE (table); i++) for (i = 0; i < (int) ARRAY_SIZE (table); i++)
if (table[i].name[0] if (table[i].name[0]
&& ! strcmp (asmspec, table[i].name)) && ! strcmp (asmspec, table[i].name)
&& reg_names[table[i].number][0])
return table[i].number; return table[i].number;
} }
#endif /* ADDITIONAL_REGISTER_NAMES */ #endif /* ADDITIONAL_REGISTER_NAMES */