git
/
gcc
mirror of git://gcc.gnu.org/git/gcc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

s390.c: (s390_adjust_priority): Adapt to changed attribute names. 

2005-05-09  Adrian Straetling  <straetling@de.ibm.com>

	* config/s390/s390.c: (s390_adjust_priority): Adapt to changed
	attribute names.
	* config/s390/2084.md: ("x_fsimpd", "x_fsimps", "x_fdivd", "x_fdivs",
	"x_floadd", "x_floads", "x_fstored", "x_fstores"): Rename to
	("x_fsimpdf", "x_fsimpsf", "x_fdivdf", "x_fdivsf", "x_floaddf",
	"x_floadsf", "x_fstoredf", "x_fstoresf") and replace 'type'
	attribute names.
	* config/s390/s390.md: ("type"): Rename "fsimpd, fsimps, floadd, floads,
	fstored, fstores, fmuld, fmuls, fdivd, fdivs, fsqrtd, fsqrts" to
	"fsimpdf, fsimpsf, floaddf, floadsf, fstoredf, fstoresf, fmuldf,
	fmulsf, fdivdf, fdivsf, fsqrtdf, fsqrtsf".
	("*cmpdf_ccs_0", "*cmpdf_css_0_ibm", "*cmpdf_ccs",
	"*cmpdf_ccs_ibm", "*cmpsf_ccs_0", "*cmpsf_css_0_ibm",
	"*cmpsf_ccs", "*cmpsf_ccs_ibm", "*movdi_64", "*movdi_31",
	"*movsi_zarch", "*movsi_esa", "*movdf_64", "*movdf_31", "movsf",
	"*muldf3", "*muldf3_ibm", "*fmadddf", "*fmsubdf", "*mulsf3",
	"mulsf3_ibm", "*fmaddsf", "fmsubsf", "*divdf3", "*divdf3_ibm",
	"*negdf2_cc", "*negdf2_cconly", "*negdf2", "*negdf2_ibm",
	"*negsf2_cc", "*negsf2_cconly", "*negsf2", "*absdf2_cc",
	"*absdf2_cconly", "*absdf2", "*absdf2_ibm", "*abssf2_cc",
	"*abssf2_cconly", "*abssf2", "*abssf2_ibm", "*negabsdf2_cc",
	"*negabsdf2_cconly", "*negabsdf2", "*negabssf2_cc",
	"*negabssf2_cconly", "*negabssf2", "sqrtdf2", "sqrtsf2"): Rename
	'type' value.
	("*divsf3"): Additionally rename second pattern to
	"*divsf3_ibm".
	("truncdfsf2_ibm", "extendsfdf2_ieee", "extendsfdf2_ibm",
	"*adddf3", "*adddf3_cc", "*adddf3_cconly", "*adddf3_ibm",
	"*addsf3", "*addsf3_cc", "*addsf3_cconly", "*subdf3",
	"subdf3_cc", "*subdf3_cconly", "*subdf3_ibm", "*subsf3",
	"subsf3_cc", "*subsf3_cconly", "*subsf3_ibm"): Merge identical
	'type values' and rename 'type' value.
	("*addsf3"): Additionally rename second pattern to
	"*addsf3_ibm".

From-SVN: r99456
This commit is contained in:
Adrian Straetling 2005-05-09 17:24:37 +00:00 committed by Ulrich Weigand
parent f337b93018
commit cfdb984baf
4 changed files with 142 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
gcc/ChangeLog
View File

@ -1,3 +1,40 @@
2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.c: (s390_adjust_priority): Adapt to changed
attribute names.
* config/s390/2084.md: ("x_fsimpd", "x_fsimps", "x_fdivd", "x_fdivs",
"x_floadd", "x_floads", "x_fstored", "x_fstores"): Rename to
("x_fsimpdf", "x_fsimpsf", "x_fdivdf", "x_fdivsf", "x_floaddf",
"x_floadsf", "x_fstoredf", "x_fstoresf") and replace 'type'
attribute names.
* config/s390/s390.md: ("type"): Rename "fsimpd, fsimps, floadd, floads,
fstored, fstores, fmuld, fmuls, fdivd, fdivs, fsqrtd, fsqrts" to
"fsimpdf, fsimpsf, floaddf, floadsf, fstoredf, fstoresf, fmuldf,
fmulsf, fdivdf, fdivsf, fsqrtdf, fsqrtsf".
("*cmpdf_ccs_0", "*cmpdf_css_0_ibm", "*cmpdf_ccs",
"*cmpdf_ccs_ibm", "*cmpsf_ccs_0", "*cmpsf_css_0_ibm",
"*cmpsf_ccs", "*cmpsf_ccs_ibm", "*movdi_64", "*movdi_31",
"*movsi_zarch", "*movsi_esa", "*movdf_64", "*movdf_31", "movsf",
"*muldf3", "*muldf3_ibm", "*fmadddf", "*fmsubdf", "*mulsf3",
"mulsf3_ibm", "*fmaddsf", "fmsubsf", "*divdf3", "*divdf3_ibm",
"*negdf2_cc", "*negdf2_cconly", "*negdf2", "*negdf2_ibm",
"*negsf2_cc", "*negsf2_cconly", "*negsf2", "*absdf2_cc",
"*absdf2_cconly", "*absdf2", "*absdf2_ibm", "*abssf2_cc",
"*abssf2_cconly", "*abssf2", "*abssf2_ibm", "*negabsdf2_cc",
"*negabsdf2_cconly", "*negabsdf2", "*negabssf2_cc",
"*negabssf2_cconly", "*negabssf2", "sqrtdf2", "sqrtsf2"): Rename
'type' value.
("*divsf3"): Additionally rename second pattern to
"*divsf3_ibm".
("truncdfsf2_ibm", "extendsfdf2_ieee", "extendsfdf2_ibm",
"*adddf3", "*adddf3_cc", "*adddf3_cconly", "*adddf3_ibm",
"*addsf3", "*addsf3_cc", "*addsf3_cconly", "*subdf3",
"subdf3_cc", "*subdf3_cconly", "*subdf3_ibm", "*subsf3",
"subsf3_cc", "*subsf3_cconly", "*subsf3_ibm"): Merge identical
'type values' and rename 'type' value.
("*addsf3"): Additionally rename second pattern to
"*addsf3_ibm".
2005-05-09 Adrian Straetling <straetling@de.ibm.com> 2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.md: ("SHIFT"): New mode macro. * config/s390/s390.md: ("SHIFT"): New mode macro.

52
gcc/config/s390/2084.md
View File

@ -156,44 +156,44 @@
;; Floating point insns ;; Floating point insns
;; ;;
(define_insn_reservation "x_fsimpd" 6 (define_insn_reservation "x_fsimpdf" 6
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "fsimpd,fmuld")) (eq_attr "type" "fsimpdf,fmuldf"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
(define_insn_reservation "x_fsimps" 6 (define_insn_reservation "x_fsimpsf" 6
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "fsimps,fmuls")) (eq_attr "type" "fsimpsf,fmulsf"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
(define_insn_reservation "x_fdivd" 36 (define_insn_reservation "x_fdivdf" 36
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "fdivd,fsqrtd")) (eq_attr "type" "fdivdf,fsqrtdf"))
"x_e1_t*30,x-wr-fp") "x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_fdivs" 36 (define_insn_reservation "x_fdivsf" 36
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "fdivs,fsqrts")) (eq_attr "type" "fdivsf,fsqrtsf"))
"x_e1_t*30,x-wr-fp") "x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_floadd" 6 (define_insn_reservation "x_floaddf" 6
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "floadd")) (eq_attr "type" "floaddf"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
(define_insn_reservation "x_floads" 6 (define_insn_reservation "x_floadsf" 6
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "floads")) (eq_attr "type" "floadsf"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
(define_insn_reservation "x_fstored" 1 (define_insn_reservation "x_fstoredf" 1
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "fstored")) (eq_attr "type" "fstoredf"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
(define_insn_reservation "x_fstores" 1 (define_insn_reservation "x_fstoresf" 1
(and (eq_attr "cpu" "z990") (and (eq_attr "cpu" "z990")
(eq_attr "type" "fstores")) (eq_attr "type" "fstoresf"))
"x_e1_t,x-wr-fp") "x_e1_t,x-wr-fp")
(define_insn_reservation "x_ftoi" 1 (define_insn_reservation "x_ftoi" 1
@ -206,13 +206,13 @@
(eq_attr "type" "itof")) (eq_attr "type" "itof"))
"x_e1_t*3,x-wr-fp") "x_e1_t*3,x-wr-fp")
(define_bypass 1 "x_fsimpd" "x_fstored") (define_bypass 1 "x_fsimpdf" "x_fstoredf")
(define_bypass 1 "x_fsimps" "x_fstores") (define_bypass 1 "x_fsimpsf" "x_fstoresf")
(define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd") (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf")
(define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads") (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf")
;; ;;
;; s390_agen_dep_p returns 1, if a register is set in the ;; s390_agen_dep_p returns 1, if a register is set in the
@ -229,8 +229,8 @@
"s390_agen_dep_p") "s390_agen_dep_p")
(define_bypass 9 "x_int,x_agen,x_lr" (define_bypass 9 "x_int,x_agen,x_lr"
"x_floadd, x_floads, x_fstored, x_fstores,\ "x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
x_fsimpd, x_fsimps, x_fdivd, x_fdivs" x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
"s390_agen_dep_p") "s390_agen_dep_p")
;; ;;
;; A load type instruction uses a bypass to feed the result back ;; A load type instruction uses a bypass to feed the result back
@ -242,8 +242,8 @@
"s390_agen_dep_p") "s390_agen_dep_p")
(define_bypass 5 "x_load" (define_bypass 5 "x_load"
"x_floadd, x_floads, x_fstored, x_fstores,\ "x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
x_fsimpd, x_fsimps, x_fdivd, x_fdivs" x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
"s390_agen_dep_p") "s390_agen_dep_p")
;; ;;
@ -256,8 +256,8 @@
"s390_agen_dep_p") "s390_agen_dep_p")
(define_bypass 5 "x_larl, x_la" (define_bypass 5 "x_larl, x_la"
"x_floadd, x_floads, x_fstored, x_fstores,\ "x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
x_fsimpd, x_fsimps, x_fdivd, x_fdivs" x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
"s390_agen_dep_p") "s390_agen_dep_p")
;; ;;

4
gcc/config/s390/s390.c
View File

@ -4211,8 +4211,8 @@ s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
switch (s390_safe_attr_type (insn)) switch (s390_safe_attr_type (insn))
{ {
case TYPE_FSTORED: case TYPE_FSTOREDF:
case TYPE_FSTORES: case TYPE_FSTORESF:
priority = priority << 3; priority = priority << 3;
break; break;
case TYPE_STORE: case TYPE_STORE:

154
gcc/config/s390/s390.md
View File

@ -158,10 +158,10 @@
(define_attr "type" "none,integer,load,lr,la,larl,lm,stm, (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
cs,vs,store,idiv, cs,vs,store,idiv,
imulhi,imulsi,imuldi, imulhi,imulsi,imuldi,
branch,jsr,fsimpd,fsimps, branch,jsr,fsimpdf,fsimpsf,
floadd,floads,fstored, fstores, floaddf,floadsf,fstoredf,fstoresf,
fmuld,fmuls,fdivd,fdivs, fmuldf,fmulsf,fdivdf,fdivsf,
ftoi,itof,fsqrtd,fsqrts, ftoi,itof,fsqrtdf,fsqrtsf,
other" other"
(cond [(eq_attr "op_type" "NN") (const_string "other") (cond [(eq_attr "op_type" "NN") (const_string "other")
(eq_attr "op_type" "SS") (const_string "cs")] (eq_attr "op_type" "SS") (const_string "cs")]
@ -701,7 +701,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltdbr\t%0,%0" "ltdbr\t%0,%0"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*cmpdf_ccs_0_ibm" (define_insn "*cmpdf_ccs_0_ibm"
[(set (reg 33) [(set (reg 33)
@ -710,7 +710,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"ltdr\t%0,%0" "ltdr\t%0,%0"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*cmpdf_ccs" (define_insn "*cmpdf_ccs"
[(set (reg 33) [(set (reg 33)
@ -721,7 +721,7 @@
cdbr\t%0,%1 cdbr\t%0,%1
cdb\t%0,%1" cdb\t%0,%1"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*cmpdf_ccs_ibm" (define_insn "*cmpdf_ccs_ibm"
[(set (reg 33) [(set (reg 33)
@ -732,7 +732,7 @@
cdr\t%0,%1 cdr\t%0,%1
cd\t%0,%1" cd\t%0,%1"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
; SF instructions ; SF instructions
@ -744,7 +744,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltebr\t%0,%0" "ltebr\t%0,%0"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*cmpsf_ccs_0_ibm" (define_insn "*cmpsf_ccs_0_ibm"
[(set (reg 33) [(set (reg 33)
@ -753,7 +753,7 @@
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lter\t%0,%0" "lter\t%0,%0"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*cmpsf_ccs" (define_insn "*cmpsf_ccs"
[(set (reg 33) [(set (reg 33)
@ -764,7 +764,7 @@
cebr\t%0,%1 cebr\t%0,%1
ceb\t%0,%1" ceb\t%0,%1"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*cmpsf_ccs" (define_insn "*cmpsf_ccs"
[(set (reg 33) [(set (reg 33)
@ -775,7 +775,7 @@
cer\t%0,%1 cer\t%0,%1
ce\t%0,%1" ce\t%0,%1"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
;; ;;
@ -904,7 +904,7 @@
[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
(set_attr "type" "*,*,*,*,*,la,lr,load,store, (set_attr "type" "*,*,*,*,*,la,lr,load,store,
floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")]) floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
@ -955,7 +955,7 @@
stdy\t%1,%0 stdy\t%1,%0
#" #"
[(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS") [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")]) (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
(define_split (define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "") [(set (match_operand:DI 0 "nonimmediate_operand" "")
@ -1119,7 +1119,7 @@
[(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY, [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
(set_attr "type" "*,*,*,la,lr,load,load,store,store, (set_attr "type" "*,*,*,la,lr,load,load,store,store,
floads,floads,floads,fstores,fstores,*,*,*,*,*")]) floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
(define_insn "*movsi_esa" (define_insn "*movsi_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
@ -1139,7 +1139,7 @@
lam\t%0,%0,%S1 lam\t%0,%0,%S1
#" #"
[(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
(set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")]) (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
@ -1396,7 +1396,7 @@
stg\t%1,%0 stg\t%1,%0
#" #"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")]) (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
(define_insn "*movdf_31" (define_insn "*movdf_31"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
@ -1414,7 +1414,7 @@
# #
#" #"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")]) (set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
(define_split (define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "") [(set (match_operand:DF 0 "nonimmediate_operand" "")
@ -1491,7 +1491,7 @@
sty\t%1,%0 sty\t%1,%0
#" #"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "floads,floads,floads,fstores,fstores, (set_attr "type" "floadsf,floadsf,floadsf,fstoresf,fstoresf,
lr,load,load,store,store,*")]) lr,load,load,store,store,*")])
; ;
@ -3074,7 +3074,7 @@
ler\t%0,%1 ler\t%0,%1
le\t%0,%1" le\t%0,%1"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "floads,floads")]) (set_attr "type" "floadsf")])
; ;
; extendsfdf2 instruction pattern(s). ; extendsfdf2 instruction pattern(s).
@ -3100,7 +3100,7 @@
ldebr\t%0,%1 ldebr\t%0,%1
ldeb\t%0,%1" ldeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "floads,floads")]) (set_attr "type" "floadsf")])
(define_insn "extendsfdf2_ibm" (define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
@ -3111,7 +3111,7 @@
sdr\t%0,%0\;ler\t%0,%1 sdr\t%0,%0\;ler\t%0,%1
sdr\t%0,%0\;le\t%0,%1" sdr\t%0,%0\;le\t%0,%1"
[(set_attr "length" "4,6") [(set_attr "length" "4,6")
(set_attr "type" "floads,floads")]) (set_attr "type" "floadsf")])
;; ;;
@ -3536,7 +3536,7 @@
adbr\t%0,%2 adbr\t%0,%2
adb\t%0,%2" adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*adddf3_cc" (define_insn "*adddf3_cc"
[(set (reg 33) [(set (reg 33)
@ -3550,7 +3550,7 @@
adbr\t%0,%2 adbr\t%0,%2
adb\t%0,%2" adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*adddf3_cconly" (define_insn "*adddf3_cconly"
[(set (reg 33) [(set (reg 33)
@ -3563,7 +3563,7 @@
adbr\t%0,%2 adbr\t%0,%2
adb\t%0,%2" adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*adddf3_ibm" (define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
@ -3575,7 +3575,7 @@
adr\t%0,%2 adr\t%0,%2
ad\t%0,%2" ad\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
; ;
; addsf3 instruction pattern(s). ; addsf3 instruction pattern(s).
@ -3600,7 +3600,7 @@
aebr\t%0,%2 aebr\t%0,%2
aeb\t%0,%2" aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*addsf3_cc" (define_insn "*addsf3_cc"
[(set (reg 33) [(set (reg 33)
@ -3614,7 +3614,7 @@
aebr\t%0,%2 aebr\t%0,%2
aeb\t%0,%2" aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*addsf3_cconly" (define_insn "*addsf3_cconly"
[(set (reg 33) [(set (reg 33)
@ -3627,9 +3627,9 @@
aebr\t%0,%2 aebr\t%0,%2
aeb\t%0,%2" aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*addsf3" (define_insn "*addsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,R"))) (match_operand:SF 2 "general_operand" "f,R")))
@ -3639,7 +3639,7 @@
aer\t%0,%2 aer\t%0,%2
ae\t%0,%2" ae\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
;; ;;
@ -4004,7 +4004,7 @@
sdbr\t%0,%2 sdbr\t%0,%2
sdb\t%0,%2" sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*subdf3_cc" (define_insn "*subdf3_cc"
[(set (reg 33) [(set (reg 33)
@ -4018,7 +4018,7 @@
sdbr\t%0,%2 sdbr\t%0,%2
sdb\t%0,%2" sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*subdf3_cconly" (define_insn "*subdf3_cconly"
[(set (reg 33) [(set (reg 33)
@ -4031,7 +4031,7 @@
sdbr\t%0,%2 sdbr\t%0,%2
sdb\t%0,%2" sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*subdf3_ibm" (define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
@ -4043,7 +4043,7 @@
sdr\t%0,%2 sdr\t%0,%2
sd\t%0,%2" sd\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimpd,fsimpd")]) (set_attr "type" "fsimpdf")])
; ;
; subsf3 instruction pattern(s). ; subsf3 instruction pattern(s).
@ -4068,7 +4068,7 @@
sebr\t%0,%2 sebr\t%0,%2
seb\t%0,%2" seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*subsf3_cc" (define_insn "*subsf3_cc"
[(set (reg 33) [(set (reg 33)
@ -4082,7 +4082,7 @@
sebr\t%0,%2 sebr\t%0,%2
seb\t%0,%2" seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*subsf3_cconly" (define_insn "*subsf3_cconly"
[(set (reg 33) [(set (reg 33)
@ -4095,7 +4095,7 @@
sebr\t%0,%2 sebr\t%0,%2
seb\t%0,%2" seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*subsf3_ibm" (define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
@ -4107,7 +4107,7 @@
ser\t%0,%2 ser\t%0,%2
se\t%0,%2" se\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimps,fsimps")]) (set_attr "type" "fsimpsf")])
;; ;;
@ -4339,7 +4339,7 @@
mdbr\t%0,%2 mdbr\t%0,%2
mdb\t%0,%2" mdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuld")]) (set_attr "type" "fmuldf")])
(define_insn "*muldf3_ibm" (define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
@ -4350,7 +4350,7 @@
mdr\t%0,%2 mdr\t%0,%2
md\t%0,%2" md\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuld")]) (set_attr "type" "fmuldf")])
(define_insn "*fmadddf" (define_insn "*fmadddf"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
@ -4362,7 +4362,7 @@
madbr\t%0,%1,%2 madbr\t%0,%1,%2
madb\t%0,%1,%2" madb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuld")]) (set_attr "type" "fmuldf")])
(define_insn "*fmsubdf" (define_insn "*fmsubdf"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
@ -4374,7 +4374,7 @@
msdbr\t%0,%1,%2 msdbr\t%0,%1,%2
msdb\t%0,%1,%2" msdb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuld")]) (set_attr "type" "fmuldf")])
; ;
; mulsf3 instruction pattern(s). ; mulsf3 instruction pattern(s).
@ -4396,7 +4396,7 @@
meebr\t%0,%2 meebr\t%0,%2
meeb\t%0,%2" meeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuls")]) (set_attr "type" "fmulsf")])
(define_insn "*mulsf3_ibm" (define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
@ -4407,7 +4407,7 @@
mer\t%0,%2 mer\t%0,%2
me\t%0,%2" me\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuls")]) (set_attr "type" "fmulsf")])
(define_insn "*fmaddsf" (define_insn "*fmaddsf"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
@ -4419,7 +4419,7 @@
maebr\t%0,%1,%2 maebr\t%0,%1,%2
maeb\t%0,%1,%2" maeb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuls")]) (set_attr "type" "fmulsf")])
(define_insn "*fmsubsf" (define_insn "*fmsubsf"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
@ -4431,7 +4431,7 @@
msebr\t%0,%1,%2 msebr\t%0,%1,%2
mseb\t%0,%1,%2" mseb\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuls")]) (set_attr "type" "fmulsf")])
;; ;;
;;- Divide and modulo instructions. ;;- Divide and modulo instructions.
@ -4889,7 +4889,7 @@
ddbr\t%0,%2 ddbr\t%0,%2
ddb\t%0,%2" ddb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fdivd")]) (set_attr "type" "fdivdf")])
(define_insn "*divdf3_ibm" (define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
@ -4900,7 +4900,7 @@
ddr\t%0,%2 ddr\t%0,%2
dd\t%0,%2" dd\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fdivd")]) (set_attr "type" "fdivdf")])
; ;
; divsf3 instruction pattern(s). ; divsf3 instruction pattern(s).
@ -4922,9 +4922,9 @@
debr\t%0,%2 debr\t%0,%2
deb\t%0,%2" deb\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fdivs")]) (set_attr "type" "fdivsf")])
(define_insn "*divsf3" (define_insn "*divsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0") (div:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,R")))] (match_operand:SF 2 "general_operand" "f,R")))]
@ -4933,7 +4933,7 @@
der\t%0,%2 der\t%0,%2
de\t%0,%2" de\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "fdivs")]) (set_attr "type" "fdivsf")])
;; ;;
@ -5913,7 +5913,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1" "lcdbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*negdf2_cconly" (define_insn "*negdf2_cconly"
[(set (reg 33) [(set (reg 33)
@ -5923,7 +5923,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1" "lcdbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*negdf2" (define_insn "*negdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
@ -5932,7 +5932,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\t%0,%1" "lcdbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*negdf2_ibm" (define_insn "*negdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
@ -5941,7 +5941,7 @@
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcdr\t%0,%1" "lcdr\t%0,%1"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
; ;
; negsf2 instruction pattern(s). ; negsf2 instruction pattern(s).
@ -5964,7 +5964,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1" "lcebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*negsf2_cconly" (define_insn "*negsf2_cconly"
[(set (reg 33) [(set (reg 33)
@ -5974,7 +5974,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1" "lcebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*negsf2" (define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
@ -5983,16 +5983,16 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\t%0,%1" "lcebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*negsf2" (define_insn "*negsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "register_operand" "f"))) (neg:SF (match_operand:SF 1 "register_operand" "f")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcer\t%0,%1" "lcer\t%0,%1"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
;; ;;
@ -6071,7 +6071,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1" "lpdbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*absdf2_cconly" (define_insn "*absdf2_cconly"
[(set (reg 33) [(set (reg 33)
@ -6081,7 +6081,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1" "lpdbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*absdf2" (define_insn "*absdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
@ -6090,7 +6090,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\t%0,%1" "lpdbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*absdf2_ibm" (define_insn "*absdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
@ -6099,7 +6099,7 @@
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lpdr\t%0,%1" "lpdr\t%0,%1"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
; ;
; abssf2 instruction pattern(s). ; abssf2 instruction pattern(s).
@ -6122,7 +6122,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1" "lpebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*abssf2_cconly" (define_insn "*abssf2_cconly"
[(set (reg 33) [(set (reg 33)
@ -6132,7 +6132,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1" "lpebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*abssf2" (define_insn "*abssf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
@ -6141,7 +6141,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\t%0,%1" "lpebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*abssf2_ibm" (define_insn "*abssf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
@ -6150,7 +6150,7 @@
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lper\t%0,%1" "lper\t%0,%1"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
;; ;;
;;- Negated absolute value instructions ;;- Negated absolute value instructions
@ -6221,7 +6221,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1" "lndbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*negabsdf2_cconly" (define_insn "*negabsdf2_cconly"
[(set (reg 33) [(set (reg 33)
@ -6231,7 +6231,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1" "lndbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*negabsdf2" (define_insn "*negabsdf2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
@ -6240,7 +6240,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\t%0,%1" "lndbr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")]) (set_attr "type" "fsimpdf")])
(define_insn "*negabssf2_cc" (define_insn "*negabssf2_cc"
[(set (reg 33) [(set (reg 33)
@ -6251,7 +6251,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1" "lnebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*negabssf2_cconly" (define_insn "*negabssf2_cconly"
[(set (reg 33) [(set (reg 33)
@ -6261,7 +6261,7 @@
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1" "lnebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
(define_insn "*negabssf2" (define_insn "*negabssf2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
@ -6270,7 +6270,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\t%0,%1" "lnebr\t%0,%1"
[(set_attr "op_type" "RRE") [(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")]) (set_attr "type" "fsimpsf")])
;; ;;
;;- Square root instructions. ;;- Square root instructions.
@ -6288,7 +6288,7 @@
sqdbr\t%0,%1 sqdbr\t%0,%1
sqdb\t%0,%1" sqdb\t%0,%1"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsqrtd")]) (set_attr "type" "fsqrtdf")])
; ;
; sqrtsf2 instruction pattern(s). ; sqrtsf2 instruction pattern(s).
@ -6302,7 +6302,7 @@
sqebr\t%0,%1 sqebr\t%0,%1
sqeb\t%0,%1" sqeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsqrts")]) (set_attr "type" "fsqrtsf")])
;; ;;
;;- One complement instructions. ;;- One complement instructions.