mirror of git://gcc.gnu.org/git/gcc.git
rs6000-protos.h (rs6000_adjust_vec_address): New function that takes a vector memory address...
[gcc] 2016-07-30 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-protos.h (rs6000_adjust_vec_address): New function that takes a vector memory address, a hard register, an element number and a temporary base register, and recreates an address that points to the appropriate element within the vector. * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Likewise. (rs6000_split_vec_extract_var): Add support for the target of a vec_extract with variable element number being a scalar memory location. (rtx_is_swappable_p): VLSO insns (UNSPEC_VSX_VSLOW) are not swappable. * config/rs6000/vsx.md (vsx_extract_<mode>_load): Replace vsx_extract_<mode>_load insn with a new insn that optimizes storing either element to a memory location, using scratch registers to pick apart the vector and reconstruct the address. (vsx_extract_<P:mode>_<VSX_D:mode>_load): Likewise. (vsx_extract_<mode>_store): Rework alternatives to more correctly support Altivec registers. Add support for ISA 3.0 Altivec d-form store instruction. (vsx_extract_<mode>_var): Add support for extracting a variable element number from memory. [gcc/testsuite] 2016-07-30 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/vec-extract-2.c: New tests for vec_extract of vector double or vector long where the vector is in memory. * gcc.target/powerpc/vec-extract-3.c: Likewise. * gcc.target/powerpc/vec-extract-4.c: Likewise. From-SVN: r238908
This commit is contained in:
Michael Meissner
Michael Meissner
parent
e4f7a5dffe
commit
d0047a2538
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@ -1,3 +1,26 @@
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2016-07-30 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/rs6000-protos.h (rs6000_adjust_vec_address): New
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function that takes a vector memory address, a hard register, an
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element number and a temporary base register, and recreates an
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address that points to the appropriate element within the vector.
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* config/rs6000/rs6000.c (rs6000_adjust_vec_address): Likewise.
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(rs6000_split_vec_extract_var): Add support for the target of a
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vec_extract with variable element number being a scalar memory
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location.
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(rtx_is_swappable_p): VLSO insns (UNSPEC_VSX_VSLOW) are not
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swappable.
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* config/rs6000/vsx.md (vsx_extract_<mode>_load): Replace
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vsx_extract_<mode>_load insn with a new insn that optimizes
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storing either element to a memory location, using scratch
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registers to pick apart the vector and reconstruct the address.
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(vsx_extract_<P:mode>_<VSX_D:mode>_load): Likewise.
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(vsx_extract_<mode>_store): Rework alternatives to more correctly
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support Altivec registers. Add support for ISA 3.0 Altivec d-form
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store instruction.
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(vsx_extract_<mode>_var): Add support for extracting a variable
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element number from memory.
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2016-07-29 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.c (avr_out_compare): Use const0_rtx instead of 0
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@ -63,6 +63,7 @@ extern void paired_expand_vector_init (rtx, rtx);
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extern void rs6000_expand_vector_set (rtx, rtx, int);
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extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
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extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
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extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode);
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extern bool altivec_expand_vec_perm_const (rtx op[4]);
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extern void altivec_expand_vec_perm_le (rtx op[4]);
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extern bool rs6000_expand_vec_perm_const (rtx op[4]);
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@ -7001,6 +7001,164 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
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emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
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}
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/* Adjust a memory address (MEM) of a vector type to point to a scalar field
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within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
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temporary (BASE_TMP) to fixup the address. Return the new memory address
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that is valid for reads or writes to a given register (SCALAR_REG). */
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rtx
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rs6000_adjust_vec_address (rtx scalar_reg,
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rtx mem,
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rtx element,
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rtx base_tmp,
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machine_mode scalar_mode)
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{
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unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
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rtx addr = XEXP (mem, 0);
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rtx element_offset;
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rtx new_addr;
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bool valid_addr_p;
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/* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
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gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
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/* Calculate what we need to add to the address to get the element
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address. */
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if (CONST_INT_P (element))
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element_offset = GEN_INT (INTVAL (element) * scalar_size);
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else
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{
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int byte_shift = exact_log2 (scalar_size);
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gcc_assert (byte_shift >= 0);
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if (byte_shift == 0)
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element_offset = element;
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else
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{
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if (TARGET_POWERPC64)
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emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
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else
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emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
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element_offset = base_tmp;
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}
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}
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/* Create the new address pointing to the element within the vector. If we
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are adding 0, we don't have to change the address. */
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if (element_offset == const0_rtx)
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new_addr = addr;
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/* A simple indirect address can be converted into a reg + offset
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address. */
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else if (REG_P (addr) || SUBREG_P (addr))
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new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
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/* Optimize D-FORM addresses with constant offset with a constant element, to
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include the element offset in the address directly. */
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else if (GET_CODE (addr) == PLUS)
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{
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rtx op0 = XEXP (addr, 0);
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rtx op1 = XEXP (addr, 1);
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rtx insn;
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gcc_assert (REG_P (op0) || SUBREG_P (op0));
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if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
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{
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HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
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rtx offset_rtx = GEN_INT (offset);
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if (IN_RANGE (offset, -32768, 32767)
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&& (scalar_size < 8 || (offset & 0x3) == 0))
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new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
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else
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{
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emit_move_insn (base_tmp, offset_rtx);
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new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
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}
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}
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else
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{
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if (REG_P (op1) || SUBREG_P (op1))
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{
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insn = gen_add3_insn (base_tmp, op1, element_offset);
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gcc_assert (insn != NULL_RTX);
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emit_insn (insn);
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}
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else if (REG_P (element_offset) || SUBREG_P (element_offset))
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{
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insn = gen_add3_insn (base_tmp, element_offset, op1);
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gcc_assert (insn != NULL_RTX);
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emit_insn (insn);
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}
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else
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{
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emit_move_insn (base_tmp, op1);
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emit_insn (gen_add2_insn (base_tmp, element_offset));
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}
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new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
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}
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}
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else
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{
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emit_move_insn (base_tmp, addr);
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new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
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}
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/* If we have a PLUS, we need to see whether the particular register class
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allows for D-FORM or X-FORM addressing. */
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if (GET_CODE (new_addr) == PLUS)
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{
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rtx op1 = XEXP (new_addr, 1);
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addr_mask_type addr_mask;
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int scalar_regno;
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if (REG_P (scalar_reg))
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scalar_regno = REGNO (scalar_reg);
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else if (SUBREG_P (scalar_reg))
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scalar_regno = subreg_regno (scalar_reg);
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else
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gcc_unreachable ();
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gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
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if (INT_REGNO_P (scalar_regno))
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addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
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else if (FP_REGNO_P (scalar_regno))
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addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
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else if (ALTIVEC_REGNO_P (scalar_regno))
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addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
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else
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gcc_unreachable ();
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if (REG_P (op1) || SUBREG_P (op1))
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valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
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else
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valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
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}
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else if (REG_P (new_addr) || SUBREG_P (new_addr))
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valid_addr_p = true;
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else
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valid_addr_p = false;
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if (!valid_addr_p)
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{
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emit_move_insn (base_tmp, new_addr);
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new_addr = base_tmp;
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}
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return change_address (mem, scalar_mode, new_addr);
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}
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/* Split a variable vec_extract operation into the component instructions. */
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void
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@ -7014,7 +7172,18 @@ rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
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gcc_assert (byte_shift >= 0);
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if (REG_P (src) || SUBREG_P (src))
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/* If we are given a memory address, optimize to load just the element. We
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don't have to adjust the vector element number on little endian
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systems. */
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if (MEM_P (src))
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{
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gcc_assert (REG_P (tmp_gpr));
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emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
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tmp_gpr, scalar_mode));
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return;
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}
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else if (REG_P (src) || SUBREG_P (src))
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{
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int bit_shift = byte_shift + 3;
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rtx element2;
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@ -38759,6 +38928,7 @@ rtx_is_swappable_p (rtx op, unsigned int *special)
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case UNSPEC_VSX_CVSPDP:
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case UNSPEC_VSX_CVSPDPN:
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case UNSPEC_VSX_EXTRACT:
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case UNSPEC_VSX_VSLO:
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return 0;
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case UNSPEC_VSPLT_DIRECT:
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*special = SH_SPLAT;
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@ -2174,33 +2174,36 @@
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}
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[(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm")])
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;; Optimize extracting a single scalar element from memory if the scalar is in
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;; the correct location to use a single load.
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(define_insn "*vsx_extract_<mode>_load"
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[(set (match_operand:<VS_scalar> 0 "register_operand" "=d,wv,wr")
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(vec_select:<VS_scalar>
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(match_operand:VSX_D 1 "memory_operand" "m,Z,m")
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(parallel [(const_int 0)])))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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"@
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lfd%U1%X1 %0,%1
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lxsd%U1x %x0,%y1
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ld%U1%X1 %0,%1"
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[(set_attr "type" "fpload,fpload,load")
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(set_attr "length" "4")])
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;; Optimize extracting a single scalar element from memory.
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(define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
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[(set (match_operand:<VS_scalar> 0 "register_operand" "=<VSX_D:VS_64reg>,wr")
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(vec_select:<VSX_D:VS_scalar>
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(match_operand:VSX_D 1 "memory_operand" "m,m")
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(parallel [(match_operand:QI 2 "const_0_to_1_operand" "n,n")])))
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(clobber (match_scratch:P 3 "=&b,&b"))]
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"VECTOR_MEM_VSX_P (<VSX_D:MODE>mode)"
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (match_dup 4))]
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{
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operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
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operands[3], <VSX_D:VS_scalar>mode);
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}
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[(set_attr "type" "fpload,load")
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(set_attr "length" "8")])
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;; Optimize storing a single scalar element that is the right location to
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;; memory
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(define_insn "*vsx_extract_<mode>_store"
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[(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,?Z")
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[(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,o")
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(vec_select:<VS_scalar>
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(match_operand:VSX_D 1 "register_operand" "d,wd,<VSa>")
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(match_operand:VSX_D 1 "register_operand" "d,wv,wb")
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(parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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"@
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stfd%U0%X0 %1,%0
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stxsd%U0x %x1,%y0
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stxsd%U0x %x1,%y0"
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stxsd %1,%0"
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[(set_attr "type" "fpstore")
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(set_attr "length" "4")])
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@ -2216,12 +2219,12 @@
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;; Variable V2DI/V2DF extract
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(define_insn_and_split "vsx_extract_<mode>_var"
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[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v")
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(unspec:<VS_scalar> [(match_operand:VSX_D 1 "input_operand" "v")
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(match_operand:DI 2 "gpc_reg_operand" "r")]
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[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v,<VSa>,r")
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(unspec:<VS_scalar> [(match_operand:VSX_D 1 "input_operand" "v,m,m")
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(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
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UNSPEC_VSX_EXTRACT))
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(clobber (match_scratch:DI 3 "=r"))
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(clobber (match_scratch:V2DI 4 "=&v"))]
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(clobber (match_scratch:DI 3 "=r,&b,&b"))
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(clobber (match_scratch:V2DI 4 "=&v,X,X"))]
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"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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@ -1,3 +1,10 @@
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2016-07-30 Michael Meissner <meissner@linux.vnet.ibm.com>
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* gcc.target/powerpc/vec-extract-2.c: New tests for vec_extract of
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vector double or vector long where the vector is in memory.
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* gcc.target/powerpc/vec-extract-3.c: Likewise.
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* gcc.target/powerpc/vec-extract-4.c: Likewise.
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2016-07-30 Steven G. Kargl <kargl@gcc.gnu.org>
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PR fortran/69867
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@ -0,0 +1,37 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-O2 -mvsx" } */
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#include <altivec.h>
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double
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add_double_0 (vector double *p, double x)
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{
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return vec_extract (*p, 0) + x;
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}
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double
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add_double_1 (vector double *p, double x)
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{
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return vec_extract (*p, 1) + x;
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}
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long
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add_long_0 (vector long *p, long x)
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{
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return vec_extract (*p, 0) + x;
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}
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long
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add_long_1 (vector long *p, long x)
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{
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return vec_extract (*p, 1) + x;
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}
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/* { dg-final { scan-assembler-not "lxvd2x" } } */
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/* { dg-final { scan-assembler-not "lxvw4x" } } */
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/* { dg-final { scan-assembler-not "lxvx" } } */
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/* { dg-final { scan-assembler-not "lxv" } } */
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/* { dg-final { scan-assembler-not "lvx" } } */
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/* { dg-final { scan-assembler-not "xxpermdi" } } */
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@ -0,0 +1,26 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-O2 -mcpu=power8" } */
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#include <altivec.h>
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double
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add_double_n (vector double *p, double x, long n)
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{
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return vec_extract (*p, n) + x;
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}
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long
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add_long_n (vector long *p, long x, long n)
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{
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return vec_extract (*p, n) + x;
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}
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/* { dg-final { scan-assembler-not "lxvd2x" } } */
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/* { dg-final { scan-assembler-not "lxvw4x" } } */
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/* { dg-final { scan-assembler-not "lxvx" } } */
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/* { dg-final { scan-assembler-not "lxv" } } */
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/* { dg-final { scan-assembler-not "lvx" } } */
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/* { dg-final { scan-assembler-not "xxpermdi" } } */
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|
|
@ -0,0 +1,23 @@
|
|||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p9vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
|
||||
/* { dg-options "-O2 -mcpu=power9" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
#define ELEMENT 1
|
||||
#else
|
||||
#define ELEMENT 0
|
||||
#endif
|
||||
|
||||
void foo (double *p, vector double v)
|
||||
{
|
||||
p[10] = vec_extract (v, ELEMENT);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "stxsd " } } */
|
||||
/* { dg-final { scan-assembler-not "stxsdx" } } */
|
||||
/* { dg-final { scan-assembler-not "stfd" } } */
|
||||
/* { dg-final { scan-assembler-not "xxpermdi" } } */
|
||||
Loading…
Reference in New Issue