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RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine 

The vwaddu and vwsubu combine pattern should take plus/minus
instead of any_widen_binop.  This PATCH would like to fix it.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Take concrete op instead
	of any_widen_binop for vwaddu/vwsubu wx combine.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2025-10-14 10:33:08 +08:00
parent 7092efd3d6
commit d58a8e37f0
1 changed files with 2 additions and 2 deletions
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4
gcc/config/riscv/autovec-opt.md
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@ -1913,7 +1913,7 @@
(define_insn_and_split "*widen_waddu_wx_<mode>"
[(set (match_operand:VWEXTI_D 0 "register_operand")
(any_widen_binop:VWEXTI_D
(plus:VWEXTI_D
(vec_duplicate:VWEXTI_D
(any_extend:<VEL>
(match_operand:<VSUBEL> 2 "register_operand")))
@ -1933,7 +1933,7 @@
(define_insn_and_split "*widen_wsubu_wx_<mode>"
[(set (match_operand:VWEXTI_D 0 "register_operand")
(any_widen_binop:VWEXTI_D
(minus:VWEXTI_D
(match_operand:VWEXTI_D 1 "register_operand")
(vec_duplicate:VWEXTI_D
(any_extend:<VEL>