mirror of git://gcc.gnu.org/git/gcc.git
rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vec_min and vec_max builtins.
[gcc] 2017-06-02 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vec_min and vec_max builtins. (builtin_function_type): Add min/max unsigned variants to those identified as having unsigned arguments. [gcc/testsuite] 2017-06-02 Will Schmidt <will_schmidt@vnet.ibm.com> * testsuite/gcc.target/powerpc/fold-vec-minmax-char.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-floatdouble.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-int.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c: New. * testsuite/gcc.target/powerpc/fold-vec-minmax-short.c: New. From-SVN: r248834
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@ -1,3 +1,9 @@
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2017-06-02 Will Schmidt <will_schmidt@vnet.ibm.com>
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* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling
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for early expansion of vec_min and vec_max builtins.
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(builtin_function_type): Add min/max unsigned variants to those
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identified as having unsigned arguments.
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2017-06-02 Olivier Hainque <hainque@adacore.com>
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* config/vx-common.h (DWARF_UNWIND_INFO): Switch #define to 1.
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@ -17347,6 +17347,46 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
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gsi_replace (gsi, g, true);
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return true;
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}
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/* flavors of vec_min. */
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case VSX_BUILTIN_XVMINDP:
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case P8V_BUILTIN_VMINSD:
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case P8V_BUILTIN_VMINUD:
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case ALTIVEC_BUILTIN_VMINSB:
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case ALTIVEC_BUILTIN_VMINSH:
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case ALTIVEC_BUILTIN_VMINSW:
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case ALTIVEC_BUILTIN_VMINUB:
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case ALTIVEC_BUILTIN_VMINUH:
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case ALTIVEC_BUILTIN_VMINUW:
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case ALTIVEC_BUILTIN_VMINFP:
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{
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arg0 = gimple_call_arg (stmt, 0);
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arg1 = gimple_call_arg (stmt, 1);
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lhs = gimple_call_lhs (stmt);
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gimple *g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
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gimple_set_location (g, gimple_location (stmt));
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gsi_replace (gsi, g, true);
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return true;
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}
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/* flavors of vec_max. */
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case VSX_BUILTIN_XVMAXDP:
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case P8V_BUILTIN_VMAXSD:
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case P8V_BUILTIN_VMAXUD:
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case ALTIVEC_BUILTIN_VMAXSB:
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case ALTIVEC_BUILTIN_VMAXSH:
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case ALTIVEC_BUILTIN_VMAXSW:
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case ALTIVEC_BUILTIN_VMAXUB:
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case ALTIVEC_BUILTIN_VMAXUH:
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case ALTIVEC_BUILTIN_VMAXUW:
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case ALTIVEC_BUILTIN_VMAXFP:
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{
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arg0 = gimple_call_arg (stmt, 0);
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arg1 = gimple_call_arg (stmt, 1);
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lhs = gimple_call_lhs (stmt);
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gimple *g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
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gimple_set_location (g, gimple_location (stmt));
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gsi_replace (gsi, g, true);
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return true;
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}
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default:
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break;
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}
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@ -18985,6 +19025,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
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case MISC_BUILTIN_DIVDEU:
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case MISC_BUILTIN_DIVDEUO:
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case VSX_BUILTIN_UDIV_V2DI:
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case ALTIVEC_BUILTIN_VMAXUB:
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case ALTIVEC_BUILTIN_VMINUB:
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case ALTIVEC_BUILTIN_VMAXUH:
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case ALTIVEC_BUILTIN_VMINUH:
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case ALTIVEC_BUILTIN_VMAXUW:
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case ALTIVEC_BUILTIN_VMINUW:
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case P8V_BUILTIN_VMAXUD:
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case P8V_BUILTIN_VMINUD:
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h.uns_p[0] = 1;
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h.uns_p[1] = 1;
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h.uns_p[2] = 1;
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@ -1,3 +1,11 @@
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2017-06-02 Will Schmidt <will_schmidt@vnet.ibm.com>
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* gcc.target/powerpc/fold-vec-minmax-char.c: New.
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* gcc.target/powerpc/fold-vec-minmax-floatdouble.c: New.
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* gcc.target/powerpc/fold-vec-minmax-int.c: New.
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* gcc.target/powerpc/fold-vec-minmax-longlong.c: New.
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* gcc.target/powerpc/fold-vec-minmax-short.c: New.
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2017-06-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: New test.
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/* Verify that overloaded built-ins for vec_min with char
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inputs produce the right results. */
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/* { dg-do compile } */
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/* { dg-require-effective-target powerpc_altivec_ok } */
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/* { dg-options "-maltivec" } */
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#include <altivec.h>
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vector signed char
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test3_min (vector signed char x, vector signed char y)
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{
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return vec_min (x, y);
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}
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vector unsigned char
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test6_min (vector unsigned char x, vector unsigned char y)
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{
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return vec_min (x, y);
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}
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vector signed char
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test3_max (vector signed char x, vector signed char y)
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{
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return vec_max (x, y);
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}
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vector unsigned char
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test6_max (vector unsigned char x, vector unsigned char y)
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{
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return vec_max (x, y);
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}
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/* { dg-final { scan-assembler-times "vminsb" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxsb" 1 } } */
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/* { dg-final { scan-assembler-times "vminub" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxub" 1 } } */
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@ -0,0 +1,37 @@
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/* Verify that overloaded built-ins for vec_max with float and
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double inputs for VSX produce the right results. */
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/* { dg-do compile } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-mvsx -O2" } */
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#include <altivec.h>
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vector float
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test1_min (vector float x, vector float y)
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{
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return vec_min (x, y);
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}
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vector double
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test2_min (vector double x, vector double y)
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{
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return vec_min (x, y);
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}
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vector float
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test1_max (vector float x, vector float y)
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{
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return vec_max (x, y);
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}
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vector double
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test2_max (vector double x, vector double y)
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{
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return vec_max (x, y);
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}
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/* { dg-final { scan-assembler-times "vminsp" 1 } } */
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/* { dg-final { scan-assembler-times "vmindp" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxsp" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxdp" 1 } } */
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/* Verify that overloaded built-ins for vec_min with int
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inputs produce the right results. */
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/* { dg-do compile } */
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/* { dg-require-effective-target powerpc_altivec_ok } */
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/* { dg-options "-maltivec -O2" } */
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#include <altivec.h>
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vector signed int
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test3_min (vector signed int x, vector signed int y)
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{
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return vec_min (x, y);
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}
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vector unsigned int
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test6_min (vector unsigned int x, vector unsigned int y)
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{
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return vec_min (x, y);
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}
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vector signed int
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test3_max (vector signed int x, vector signed int y)
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{
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return vec_max (x, y);
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}
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vector unsigned int
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test6_max (vector unsigned int x, vector unsigned int y)
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{
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return vec_max (x, y);
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}
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/* { dg-final { scan-assembler-times "vminsw" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxsw" 1 } } */
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/* { dg-final { scan-assembler-times "vminuw" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxuw" 1 } } */
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/* Verify that overloaded built-ins for vec_min with long long
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inputs produce the right results. */
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/* { dg-do compile } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-options "-mpower8-vector" } */
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#include <altivec.h>
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vector signed long long
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test3_min (vector signed long long x, vector signed long long y)
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{
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return vec_min (x, y);
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}
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vector unsigned long long
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test6_min (vector unsigned long long x, vector unsigned long long y)
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{
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return vec_min (x, y);
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}
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vector signed long long
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test3_max (vector signed long long x, vector signed long long y)
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{
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return vec_max (x, y);
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}
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vector unsigned long long
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test6_max (vector unsigned long long x, vector unsigned long long y)
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{
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return vec_max (x, y);
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}
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/* { dg-final { scan-assembler-times "vminsd" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxsd" 1 } } */
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/* { dg-final { scan-assembler-times "vminud" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxud" 1 } } */
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/* Verify that overloaded built-ins for vec_min with short
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inputs produce the right results. */
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/* { dg-do compile } */
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/* { dg-require-effective-target powerpc_altivec_ok } */
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/* { dg-options "-maltivec" } */
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#include <altivec.h>
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vector signed short
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test3_min (vector signed short x, vector signed short y)
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{
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return vec_min (x, y);
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}
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vector unsigned short
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test6_min (vector unsigned short x, vector unsigned short y)
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{
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return vec_min (x, y);
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}
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vector signed short
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test3_max (vector signed short x, vector signed short y)
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{
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return vec_max (x, y);
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}
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vector unsigned short
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test6_max (vector unsigned short x, vector unsigned short y)
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{
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return vec_max (x, y);
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}
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/* { dg-final { scan-assembler-times "vminsh" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxsh" 1 } } */
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/* { dg-final { scan-assembler-times "vminuh" 1 } } */
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/* { dg-final { scan-assembler-times "vmaxuh" 1 } } */
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