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mn10300: Emit clr. 

From-SVN: r168722
This commit is contained in:
Richard Henderson 2011-01-12 09:51:40 -08:00 committed by Richard Henderson
parent ec815d657b
commit d84760c980
2 changed files with 32 additions and 0 deletions
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3
gcc/ChangeLog
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@ -1,5 +1,8 @@
2011-01-12 Richard Henderson <rth@redhat.com> 2011-01-12 Richard Henderson <rth@redhat.com>
* config/mn10300/mn10300.md (INT): New mode iterator.
(*mov<INT>_clr): New pattern, and peep2 to generate it.
* config/mn10300/mn10300.c (mn10300_option_override): Force enable * config/mn10300/mn10300.c (mn10300_option_override): Force enable
flag_split_wide_types. flag_split_wide_types.

29
gcc/config/mn10300/mn10300.md
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@ -68,8 +68,13 @@
] ]
(const_int 0)) (const_int 0))
) )
(define_mode_iterator INT [QI HI SI])
;; ----------------------------------------------------------------------
;; Pipeline description. ;; Pipeline description.
;; ----------------------------------------------------------------------
;; The AM33 only has a single pipeline. It has five stages (fetch, ;; The AM33 only has a single pipeline. It has five stages (fetch,
;; decode, execute, memory access, writeback) each of which normally ;; decode, execute, memory access, writeback) each of which normally
@ -1172,6 +1177,30 @@
[(set_attr "timings" "11,11,11,11,11,11,22")] [(set_attr "timings" "11,11,11,11,11,11,22")]
) )
;; If the flags register is not live, generate CLR instead of MOV 0.
;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal
;; but not a win for ADDRESS_REGS.
(define_peephole2
[(set (match_operand:INT 0 "register_operand" "") (const_int 0))]
"peep2_regno_dead_p (0, CC_REG)
&& (REGNO_DATA_P (REGNO (operands[0]), 1)
|| REGNO_EXTENDED_P (REGNO (operands[0]), 1))"
[(parallel [(set (match_dup 0) (const_int 0))
(clobber (reg:CC CC_REG))])]
)
(define_insn "*mov<mode>_clr"
[(set (match_operand:INT 0 "register_operand" "=D")
(const_int 0))
(clobber (reg:CC CC_REG))]
""
"clr %0"
)
;; ----------------------------------------------------------------------
;; ADD INSTRUCTIONS
;; ----------------------------------------------------------------------
(define_insn "*mn10300_addsi3" (define_insn "*mn10300_addsi3"
[(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,!*y,!dax") [(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,!*y,!dax")
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax") (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")