mirror of git://gcc.gnu.org/git/gcc.git
rs6000.md (UNSPEC constants): Add UNSPEC_STFIWX.
* config/rs6000/rs6000.md (UNSPEC constants): Add UNSPEC_STFIWX. (fix_truncdfsi2): Allow registers or memory as destination. When TARGET_PPC_GFXOPT, generate simplified pattern. (fix_truncdfsi2_internal): Use define_insn_and_split. (fix_truncdfsi2_internal_gfxopt): New. (fctiwz): Don't confuse register allocation by giving it no choices. (stfiwx): New. * config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Add 'Z'. (EXTRA_MEMORY_CONSTRAINT): Likewise. * config/rs6000/rs6000.c (indexed_or_indirect_operand): New. * config/rs6000/rs6000-protos.h (indexed_or_indirect_operand): New. From-SVN: r97058
This commit is contained in:
Geoffrey Keating
Geoffrey Keating
parent
86f1f8581b
commit
da4c340cc5
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@ -1,3 +1,17 @@
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2005-03-25 Geoffrey Keating <geoffk@apple.com>
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* config/rs6000/rs6000.md (UNSPEC constants): Add UNSPEC_STFIWX.
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(fix_truncdfsi2): Allow registers or memory as destination.
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When TARGET_PPC_GFXOPT, generate simplified pattern.
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(fix_truncdfsi2_internal): Use define_insn_and_split.
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(fix_truncdfsi2_internal_gfxopt): New.
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(fctiwz): Don't confuse register allocation by giving it no choices.
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(stfiwx): New.
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* config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Add 'Z'.
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(EXTRA_MEMORY_CONSTRAINT): Likewise.
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* config/rs6000/rs6000.c (indexed_or_indirect_operand): New.
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* config/rs6000/rs6000-protos.h (indexed_or_indirect_operand): New.
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2005-03-25 Kazu Hirata <kazu@cs.umass.edu>
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* dominance.c (free_dominance_info): Speed up by freeing et
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@ -49,6 +49,7 @@ extern bool rs6000_legitimate_offset_address_p (enum machine_mode, rtx, int);
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extern rtx rs6000_got_register (rtx);
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extern rtx find_addr_reg (rtx);
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extern int word_offset_memref_operand (rtx, enum machine_mode);
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extern int indexed_or_indirect_operand (rtx, enum machine_mode);
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extern rtx gen_easy_vector_constant_add_self (rtx);
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extern const char *output_vec_const_move (rtx *);
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extern void build_mask64_2_operands (rtx, rtx *);
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@ -2297,6 +2297,25 @@ word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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return (off % 4) == 0;
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}
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/* Return true if the operand is an indirect or indexed memory operand. */
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int
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indexed_or_indirect_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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rtx addr;
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if (!memory_operand (op, mode))
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return 0;
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addr = XEXP (op, 0);
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if (GET_CODE (addr) == REG)
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return 1;
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if (GET_CODE (addr) == PLUS
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&& GET_CODE (XEXP (addr, 0)) == REG
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&& GET_CODE (XEXP (addr, 1)) == REG)
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return 1;
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return 0;
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}
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/* Return true if either operand is a general purpose register. */
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bool
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@ -1357,6 +1357,7 @@ enum reg_class
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'U' is for V.4 small data references.
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'W' is a vector constant that can be easily generated (no mem refs).
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'Y' is a indexed or word-aligned displacement memory operand.
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'Z' is an indexed or indirect memory operand.
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't' is for AND masks that can be performed by two rldic{l,r} insns. */
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#define EXTRA_CONSTRAINT(OP, C) \
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@ -1372,6 +1373,7 @@ enum reg_class
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&& !mask64_operand (OP, DImode)) \
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: (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
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: (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
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: (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \
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: 0)
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/* Define which constraints are memory constraints. Tell reload
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@ -1379,7 +1381,7 @@ enum reg_class
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memory address into a base register if required. */
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#define EXTRA_MEMORY_CONSTRAINT(C, STR) \
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((C) == 'Q' || (C) == 'Y')
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((C) == 'Q' || (C) == 'Y' || (C) == 'Z')
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/* Given an rtx X being reloaded into a reg required to be
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in class CLASS, return the class of reg to actually use.
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@ -51,6 +51,7 @@
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(UNSPEC_TLSTLS 29)
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(UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
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(UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
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(UNSPEC_STFIWX 32)
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])
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;;
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@ -5272,7 +5273,7 @@
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}")
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(define_expand "fix_truncdfsi2"
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[(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
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[(parallel [(set (match_operand:SI 0 "reg_or_mem_operand" "")
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
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(clobber (match_dup 2))
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(clobber (match_dup 3))])]
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@ -5286,28 +5287,29 @@
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DONE;
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}
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operands[2] = gen_reg_rtx (DImode);
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if (TARGET_PPC_GFXOPT)
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{
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rtx orig_dest = operands[0];
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if (GET_CODE (orig_dest) != MEM)
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operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
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emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
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operands[2]));
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if (operands[0] != orig_dest)
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emit_move_insn (orig_dest, operands[0]);
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DONE;
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}
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operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
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}")
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(define_insn "*fix_truncdfsi2_internal"
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(define_insn_and_split "*fix_truncdfsi2_internal"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
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(clobber (match_operand:DI 3 "memory_operand" "=o"))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
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"#"
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[(set_attr "length" "16")])
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(define_split
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" ""))
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(clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" ""))
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(clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
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"&& 1"
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[(pc)]
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"
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{
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rtx lowword;
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@ -5321,20 +5323,47 @@
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emit_move_insn (operands[3], operands[2]);
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emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
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DONE;
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}")
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}"
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[(set_attr "length" "16")])
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(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
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[(set (match_operand:SI 0 "memory_operand" "=Z")
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
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&& TARGET_PPC_GFXOPT"
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"#"
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"&& 1"
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[(pc)]
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"
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{
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emit_insn (gen_fctiwz (operands[2], operands[1]));
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emit_insn (gen_stfiwx (operands[0], operands[2]));
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DONE;
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}"
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[(set_attr "length" "16")])
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; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
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; rather than (set (subreg:SI (reg)) (fix:SI ...))
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; because the first makes it clear that operand 0 is not live
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; before the instruction.
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(define_insn "fctiwz"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
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(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
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UNSPEC_FCTIWZ))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
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"{fcirz|fctiwz} %0,%1"
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[(set_attr "type" "fp")])
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; An UNSPEC is used so we don't have to support SImode in FP registers.
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(define_insn "stfiwx"
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[(set (match_operand:SI 0 "memory_operand" "=Z")
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(unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
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UNSPEC_STFIWX))]
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"TARGET_PPC_GFXOPT"
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"stfiwx %1,%y0"
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[(set_attr "type" "fpstore")])
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(define_expand "floatsisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
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@ -1,3 +1,7 @@
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2005-03-25 Geoffrey Keating <geoffk@apple.com>
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* gcc.dg/ppc-stfiwx.c: New.
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2005-03-25 Steve Ellcey <sje@cup.hp.com>
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PR target/19888
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@ -0,0 +1,8 @@
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/* { dg-do compile { target powerpc*-*-* } } */
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/* { dg-options "-mpowerpc-gfxopt" } */
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/* { dg-final { scan-assembler "stfiwx" } } */
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int foo (double x)
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{
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return x;
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}
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