m32r.c: Fix comment typos.

* config/m32r/m32r.c: Fix comment typos.
	* config/m68hc11/m68hc11.c: Likewise.
	* config/m68hc11/m68hc11.h: Likewise.
	* config/m68k/m68k.c: Likewise.
	* config/mcore/mcore.c: Likewise.
	* config/mcore/mcore.h: Likewise.
	* config/mcore/mcore.md: Likewise.
	* config/mips/mips.c: Likewise.
	* config/mips/mips.h: Likewise.
	* config/mips/mips.md: Likewise.
	* config/mips/netbsd.h: Likewise.
	* config/mn10300/mn10300.c: Likewise.

From-SVN: r68876

gcc/ChangeLog

@@ -1,3 +1,18 @@
+2003-07-03  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* config/m32r/m32r.c: Fix comment typos.
+	* config/m68hc11/m68hc11.c: Likewise.
+	* config/m68hc11/m68hc11.h: Likewise.
+	* config/m68k/m68k.c: Likewise.
+	* config/mcore/mcore.c: Likewise.
+	* config/mcore/mcore.h: Likewise.
+	* config/mcore/mcore.md: Likewise.
+	* config/mips/mips.c: Likewise.
+	* config/mips/mips.h: Likewise.
+	* config/mips/mips.md: Likewise.
+	* config/mips/netbsd.h: Likewise.
+	* config/mn10300/mn10300.c: Likewise.
+
 2003-07-03  Andreas Schwab  <schwab@suse.de>
 
 	* dbxout.c (pending_bincls): Move decl down inside

gcc/config/m32r/m32r.c

@@ -1028,7 +1028,7 @@ m32r_pass_by_reference (type)
 /* X and Y are two things to compare using CODE.  Emit the compare insn and
    return the rtx for compare [arg0 of the if_then_else].
    If need_compare is true then the comparison insn must be generated, rather
-   than being susummed into the following branch instruction.  */
+   than being subsumed into the following branch instruction.  */
 
 rtx
 gen_compare (code, x, y, need_compare)
@@ -1307,7 +1307,7 @@ gen_split_move_double (operands)
 		ld r1,r3+; ld r2,r3
 
 	     if r3 were not used subsequently.  However, the REG_NOTES aren't
-	     propigated correctly by the reload phase, and it can cause bad
+	     propagated correctly by the reload phase, and it can cause bad
 	     code to be generated.  We could still try:
 
 		ld r1,r3+; ld r2,r3; addi r3,-4
@@ -1334,7 +1334,7 @@ gen_split_move_double (operands)
 	st r1,r3; st r2,+r3
 
      if r3 were not used subsequently.  However, the REG_NOTES aren't
-     propigated correctly by the reload phase, and it can cause bad
+     propagated correctly by the reload phase, and it can cause bad
      code to be generated.  We could still try:
 
 	st r1,r3; st r2,+r3; addi r3,-4
@@ -1579,7 +1579,7 @@ m32r_sched_reorder (stream, verbose, ready, n_readyp, clock)
       rtx * new_tail = new_head + (n_ready - 1);
       int   i;
 
-      /* Loop through the instructions, classifing them as short/long.  Try
+      /* Loop through the instructions, classifying them as short/long.  Try
 	 to keep 2 short together and/or 1 long.  Note, the ready list is
 	 actually ordered backwards, so keep it in that manner.  */
       for (i = n_ready-1; i >= 0; i--)
@@ -2586,7 +2586,7 @@ conditional_move_operand (operand, mode)
   if (mode != SImode && mode != HImode && mode != QImode)
     return FALSE;
 
-  /* At the moment we can hanndle moving registers and loading constants.  */
+  /* At the moment we can handle moving registers and loading constants.  */
   /* To be added: Addition/subtraction/bitops/multiplication of registers.  */
 
   switch (GET_CODE (operand))
@@ -2728,7 +2728,7 @@ block_move_call (dest_reg, src_reg, bytes_rtx)
 
 /* The maximum number of bytes to copy using pairs of load/store instructions.
    If a block is larger than this then a loop will be generated to copy
-   MAX_MOVE_BYTES chunks at a time.  The value of 32 is a semi-arbitary choice.
+   MAX_MOVE_BYTES chunks at a time.  The value of 32 is a semi-arbitrary choice.
    A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
    string copy in it.  */
 #define MAX_MOVE_BYTES 32
@@ -2788,7 +2788,7 @@ m32r_expand_block_move (operands)
       /* If we are going to have to perform this loop more than
 	 once, then generate a label and compute the address the
 	 source register will contain upon completion of the final
-	 itteration.  */
+	 iteration.  */
       if (bytes > MAX_MOVE_BYTES)
 	{
 	  final_src = gen_reg_rtx (Pmode);

gcc/config/m68hc11/m68hc11.c

@@ -2366,7 +2366,7 @@ print_operand (file, op, letter)
 }
 
 /* Returns true if the operand 'op' must be printed with parenthesis
-   arround it.  This must be done only if there is a symbol whose name
+   around it.  This must be done only if there is a symbol whose name
    is a processor register.  */
 static int
 must_parenthesize (op)
@@ -4881,7 +4881,7 @@ m68hc11_find_z_replacement (insn, info)
 /* The insn uses the Z register.  Find a replacement register for it
    (either X or Y) and replace it in the insn and the next ones until
    the flow changes or the replacement register is used.  Instructions
-   are emited before and after the Z-block to preserve the value of
+   are emitted before and after the Z-block to preserve the value of
    Z and of the replacement register.  */
 
 static void

gcc/config/m68hc11/m68hc11.h

@@ -1617,7 +1617,7 @@ do {                                                                    \
 
 /* Assembler Commands for Exception Regions.  */
 
-/* Default values provided by GCC should be ok. Assumming that DWARF-2
+/* Default values provided by GCC should be ok. Assuming that DWARF-2
    frame unwind info is ok for this platform.  */
 
 #undef PREFERRED_DEBUGGING_TYPE

gcc/config/m68k/m68k.c

@@ -3388,7 +3388,7 @@ const_sint32_operand (op, mode)
 
 /* Operand predicates for implementing asymmetric pc-relative addressing
    on m68k.  The m68k supports pc-relative addressing (mode 7, register 2)
-   when used as a source operand, but not as a destintation operand.
+   when used as a source operand, but not as a destination operand.
 
    We model this by restricting the meaning of the basic predicates
    (general_operand, memory_operand, etc) to forbid the use of this

gcc/config/mcore/mcore.c

@@ -2370,7 +2370,7 @@ mcore_setup_incoming_varargs (args_so_far, mode, type, ptr_pretend_size)
      registers during the prologue.  */
   number_of_regs_before_varargs = args_so_far + mcore_num_arg_regs (mode, type);
   
-  /* There is a bug somwehere in the arg handling code.
+  /* There is a bug somewhere in the arg handling code.
      Until I can find it this workaround always pushes the
      last named argument onto the stack.  */
   number_of_regs_before_varargs = args_so_far;
@@ -2586,7 +2586,7 @@ mcore_expand_epilog ()
     }
 
   /* Give back anything else.  */
-  /* XXX: Should accumuate total and then give it back.  */
+  /* XXX: Should accumulate total and then give it back.  */
   while (growth >= 0)
     output_stack_adjust ( 1, fi.growth[growth--]);
 }
@@ -3147,7 +3147,7 @@ mcore_must_pass_on_stack (mode, type)
   if (type == NULL)
     return 0;
 
-  /* If the argugment can have its address taken, it must
+  /* If the argument can have its address taken, it must
      be placed on the stack.  */
   if (TREE_ADDRESSABLE (type))
     return 1;
@@ -3280,7 +3280,7 @@ mcore_function_arg (cum, mode, type, named)
 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
    Returns the number of argument registers required to hold *part* of
    a parameter of machine mode MODE and type TYPE (which may be NULL if
-   the type is not known).  If the argument fits entirly in the argument
+   the type is not known).  If the argument fits entirely in the argument
    registers, or entirely on the stack, then 0 is returned.  CUM is the
    number of argument registers already used by earlier parameters to
    the function.  */

gcc/config/mcore/mcore.h

@@ -258,7 +258,7 @@ extern const char * mcore_stack_increment_string;
 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 #define PARM_BOUNDARY  	32
 
-/* Doubles must be alogned to an 8 byte boundary.  */
+/* Doubles must be aligned to an 8 byte boundary.  */
 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
   ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
    ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
@@ -790,7 +790,7 @@ extern const enum reg_class reg_class_from_letter[];
 /* Output assembler code for a block containing the constant parts
    of a trampoline, leaving space for the variable parts.
 
-   On the MCore, the trapoline looks like:
+   On the MCore, the trampoline looks like:
    	lrw	r1,  function
      	lrw	r13, area
    	jmp	r13

gcc/config/mips/mips.c

@@ -1141,7 +1141,7 @@ mips_classify_address (info, x, mode, strict, lea_p)
       return ADDRESS_INVALID;
 
     case CONST_INT:
-      /* Small-integer addressses don't occur very often, but they
+      /* Small-integer addresses don't occur very often, but they
 	 are legitimate if $0 is a valid base register.  */
       if (!TARGET_MIPS16 && SMALL_INT (x))
 	return ADDRESS_CONST_INT;
@@ -1591,7 +1591,7 @@ cmp_op (op, mode)
 }
 
 /* Return nonzero if the code is a relational operation suitable for a
-   conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
+   conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
    We need this in the insn that expands `trap_if' in order to prevent
    combine from erroneously altering the condition.  */
 
@@ -3927,7 +3927,7 @@ mips_arg_info (cum, mode, type, named, info)
 			|| TREE_CODE (type) == QUAL_UNION_TYPE));
 
   /* Decide whether this argument should go in a floating-point register,
-     assuming one is free.  Later code checks for availablity.  */
+     assuming one is free.  Later code checks for availability.  */
 
   info->fpr_p = false;
   if (GET_MODE_CLASS (mode) == MODE_FLOAT
@@ -7808,7 +7808,7 @@ mips_select_rtx_section (mode, x, align)
     {
       /* For hosted applications, always put constants in small data if
 	 possible, as this gives the best performance.  */
-      /* ??? Consider using mergable small data sections.  */
+      /* ??? Consider using mergeable small data sections.  */
 
       if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
 	  && mips_section_threshold > 0)
@@ -7985,18 +7985,18 @@ mips_encode_section_info (decl, rtl, first)
          There are three cases to consider:
 
             - o32 PIC (either with or without explicit relocs)
-            - n32/n64 PIC without explict relocs
+            - n32/n64 PIC without explicit relocs
             - n32/n64 PIC with explicit relocs
 
          In the first case, both local and global accesses will use an
          R_MIPS_GOT16 relocation.  We must correctly predict which of
          the two semantics (local or global) the assembler and linker
          will apply.  The choice doesn't depend on the symbol's
-         visibility, so we deliberately ignore decl_visiblity and
+         visibility, so we deliberately ignore decl_visibility and
          binds_local_p here.
 
          In the second case, the assembler will not use R_MIPS_GOT16
-         relocations, but it chooses between local and global accessees
+         relocations, but it chooses between local and global accesses
          in the same way as for o32 PIC.
 
          In the third case we have more freedom since both forms of
@@ -8519,7 +8519,7 @@ mips16_fp_args (file, fp_code, from_fp_p)
 }
 
 /* Build a mips16 function stub.  This is used for functions which
-   take aruments in the floating point registers.  It is 32 bit code
+   take arguments in the floating point registers.  It is 32 bit code
    that moves the floating point args into the general registers, and
    then jumps to the 16 bit code.  */
 

gcc/config/mips/mips.h

@@ -1622,7 +1622,7 @@ do {							\
    done, NIL if none.
 
    When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
-   moves.  All other referces are zero extended.  */
+   moves.  All other references are zero extended.  */
 #define LOAD_EXTEND_OP(MODE) \
   (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
    ? SIGN_EXTEND : ZERO_EXTEND)
@@ -1732,7 +1732,7 @@ do {							\
    all the FIXED_REGISTERS.  Until this problem has been
    resolved this macro can be used to overcome this situation.
    In particular, block_propagate() requires this list
-   be acurate, or we can remove registers which should be live.
+   be accurate, or we can remove registers which should be live.
    This macro is used in regs_invalidated_by_call.  */
 
 
@@ -2382,7 +2382,7 @@ extern enum reg_class mips_char_to_class[256];
 /* The return address for the current frame is in r31 if this is a leaf
    function.  Otherwise, it is on the stack.  It is at a variable offset
    from sp/fp/ap, so we define a fake hard register rap which is a
-   poiner to the return address on the stack.  This always gets eliminated
+   pointer to the return address on the stack.  This always gets eliminated
    during reload to be either the frame pointer or the stack pointer plus
    an offset.  */
 

gcc/config/mips/mips.md

@@ -8819,7 +8819,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 
 ;; call_insn_operand will only accepts constant addresses if a direct
 ;; jump is acceptable.  Since the 'S' constraint is defined in terms of
-;; call_insn_operand, the same is true of the contraints.
+;; call_insn_operand, the same is true of the constraints.
 
 ;; When we use an indirect jump, we need a register that will be
 ;; preserved by the epilogue.  Since TARGET_ABICALLS forces us to

gcc/config/mips/netbsd.h

@@ -58,7 +58,7 @@ Boston, MA 02111-1307, USA.  */
    them here.  Note this is structured for easy comparison to the version
    in mips.h.
 
-   FIXME: This probably isn't the best solution.  But in the absense
+   FIXME: This probably isn't the best solution.  But in the absence
    of something better, it will have to do, for now.  */
 
 #undef TARGET_CPU_CPP_BUILTINS

gcc/config/mn10300/mn10300.c

@@ -581,7 +581,7 @@ expand_epilogue ()
      Else leave it alone, it will be cut back as part of the
      ret/retf instruction, or there wasn't any stack to begin with.
 
-     Under no circumstanes should the register save area be
+     Under no circumstances should the register save area be
      deallocated here, that would leave a window where an interrupt
      could occur and trash the register save area.  */
   if (frame_pointer_needed)