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[AArch64] Add const_offset field to aarch64_address_info 

This patch records the integer value of the address offset in
aarch64_address_info, so that it doesn't need to be re-extracted
from the rtx.  The SVE port will make more use of this.  The patch
also uses poly_int64 routines to manipulate the offset, rather than
just handling CONST_INTs.

2018-01-11  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_address_info): Add a const_offset
	field.
	(aarch64_classify_address): Initialize it.  Track polynomial offsets.
	(aarch64_print_address_internal): Use it to check for a zero offset.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r256534
This commit is contained in:
Richard Sandiford 2018-01-11 13:18:23 +00:00 committed by Richard Sandiford
parent 6a70badb2c
commit dc6401818b
2 changed files with 21 additions and 9 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
* config/aarch64/aarch64.c (aarch64_address_info): Add a const_offset
field.
(aarch64_classify_address): Initialize it. Track polynomial offsets.
(aarch64_print_address_internal): Use it to check for a zero offset.
2018-01-11 Richard Sandiford <richard.sandiford@linaro.org> 2018-01-11 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com> Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com> David Sherwood <david.sherwood@arm.com>

21
gcc/config/aarch64/aarch64.c
View File

@ -113,6 +113,7 @@ struct aarch64_address_info {
enum aarch64_address_type type; enum aarch64_address_type type;
rtx base; rtx base;
rtx offset; rtx offset;
poly_int64 const_offset;
int shift; int shift;
enum aarch64_symbol_type symbol_type; enum aarch64_symbol_type symbol_type;
}; };
@ -4545,6 +4546,8 @@ aarch64_classify_address (struct aarch64_address_info *info,
{ {
enum rtx_code code = GET_CODE (x); enum rtx_code code = GET_CODE (x);
rtx op0, op1; rtx op0, op1;
poly_int64 offset;
HOST_WIDE_INT const_size; HOST_WIDE_INT const_size;
/* On BE, we use load/store pair for all large int mode load/stores. /* On BE, we use load/store pair for all large int mode load/stores.
@ -4573,6 +4576,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
info->type = ADDRESS_REG_IMM; info->type = ADDRESS_REG_IMM;
info->base = x; info->base = x;
info->offset = const0_rtx; info->offset = const0_rtx;
info->const_offset = 0;
return aarch64_base_register_rtx_p (x, strict_p); return aarch64_base_register_rtx_p (x, strict_p);
case PLUS: case PLUS:
@ -4582,24 +4586,24 @@ aarch64_classify_address (struct aarch64_address_info *info,
if (! strict_p if (! strict_p
&& REG_P (op0) && REG_P (op0)
&& virt_or_elim_regno_p (REGNO (op0)) && virt_or_elim_regno_p (REGNO (op0))
&& CONST_INT_P (op1)) && poly_int_rtx_p (op1, &offset))
{ {
info->type = ADDRESS_REG_IMM; info->type = ADDRESS_REG_IMM;
info->base = op0; info->base = op0;
info->offset = op1; info->offset = op1;
info->const_offset = offset;
return true; return true;
} }
if (maybe_ne (GET_MODE_SIZE (mode), 0) if (maybe_ne (GET_MODE_SIZE (mode), 0)
&& CONST_INT_P (op1) && aarch64_base_register_rtx_p (op0, strict_p)
&& aarch64_base_register_rtx_p (op0, strict_p)) && poly_int_rtx_p (op1, &offset))
{ {
HOST_WIDE_INT offset = INTVAL (op1);
info->type = ADDRESS_REG_IMM; info->type = ADDRESS_REG_IMM;
info->base = op0; info->base = op0;
info->offset = op1; info->offset = op1;
info->const_offset = offset;
/* TImode and TFmode values are allowed in both pairs of X /* TImode and TFmode values are allowed in both pairs of X
registers and individual Q registers. The available registers and individual Q registers. The available
@ -4679,13 +4683,12 @@ aarch64_classify_address (struct aarch64_address_info *info,
info->type = ADDRESS_REG_WB; info->type = ADDRESS_REG_WB;
info->base = XEXP (x, 0); info->base = XEXP (x, 0);
if (GET_CODE (XEXP (x, 1)) == PLUS if (GET_CODE (XEXP (x, 1)) == PLUS
&& CONST_INT_P (XEXP (XEXP (x, 1), 1)) && poly_int_rtx_p (XEXP (XEXP (x, 1), 1), &offset)
&& rtx_equal_p (XEXP (XEXP (x, 1), 0), info->base) && rtx_equal_p (XEXP (XEXP (x, 1), 0), info->base)
&& aarch64_base_register_rtx_p (info->base, strict_p)) && aarch64_base_register_rtx_p (info->base, strict_p))
{ {
HOST_WIDE_INT offset;
info->offset = XEXP (XEXP (x, 1), 1); info->offset = XEXP (XEXP (x, 1), 1);
offset = INTVAL (info->offset); info->const_offset = offset;
/* TImode and TFmode values are allowed in both pairs of X /* TImode and TFmode values are allowed in both pairs of X
registers and individual Q registers. The available registers and individual Q registers. The available
@ -5735,7 +5738,7 @@ aarch64_print_address_internal (FILE *f, machine_mode mode, rtx x,
switch (addr.type) switch (addr.type)
{ {
case ADDRESS_REG_IMM: case ADDRESS_REG_IMM:
if (addr.offset == const0_rtx) if (known_eq (addr.const_offset, 0))
asm_fprintf (f, "[%s]", reg_names [REGNO (addr.base)]); asm_fprintf (f, "[%s]", reg_names [REGNO (addr.base)]);
else else
asm_fprintf (f, "[%s, %wd]", reg_names [REGNO (addr.base)], asm_fprintf (f, "[%s, %wd]", reg_names [REGNO (addr.base)],