git
/
gcc
mirror of git://gcc.gnu.org/git/gcc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

predicates.md (const_0_to_12_operand): Rename predicate and change test from 0..11 to 0..12 to match the semantics of... 

[gcc]
2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (const_0_to_12_operand): Rename
	predicate and change test from 0..11 to 0..12 to match the
	semantics of the word extract/insert instructions.  Change all
	callers.
	(const_0_to_11_operand): Likewise.
	* config/rs6000/rs6000.c (altivec_expand_builtin): Likewise.
	* config/rs6000/vsx.md (vextract4b): Likewise.
	(vextract4b_internal): Likewise.
	(vinsert4b): Likewise.
	(vinsert4b_internal): Likewise.
	(vinsert4b_di): Likewise.
	(vinsert4b_di_internal): Likewise.
	* config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used
	in xxextractuw to zero extend the word in the vector registers.
	(lfiwzx): Likewise.

[gcc/testsuite]
2016-12-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13
	being out of bounds instead of 12.

From-SVN: r243948
This commit is contained in:
Michael Meissner 2016-12-27 23:19:15 +00:00 committed by Michael Meissner
parent 41a38208bc
commit df3aba14ab
7 changed files with 39 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
gcc/ChangeLog
View File

@ -1,3 +1,21 @@
2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (const_0_to_12_operand): Rename
predicate and change test from 0..11 to 0..12 to match the
semantics of the word extract/insert instructions. Change all
callers.
(const_0_to_11_operand): Likewise.
* config/rs6000/rs6000.c (altivec_expand_builtin): Likewise.
* config/rs6000/vsx.md (vextract4b): Likewise.
(vextract4b_internal): Likewise.
(vinsert4b): Likewise.
(vinsert4b_internal): Likewise.
(vinsert4b_di): Likewise.
(vinsert4b_di_internal): Likewise.
* config/rs6000/rs6000.md (zero_extendsi<mode>2): Fix offset used
in xxextractuw to zero extend the word in the vector registers.
(lfiwzx): Likewise.
2016-12-27 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (ix86_secondary_reload): Require QImode

4
gcc/config/rs6000/predicates.md
View File

@ -211,9 +211,9 @@
(match_test "IN_RANGE (INTVAL (op), 0, 7)")))
;; Match op = 0..11
(define_predicate "const_0_to_11_operand"
(define_predicate "const_0_to_12_operand"
(and (match_code "const_int")
(match_test "IN_RANGE (INTVAL (op), 0, 11)")))
(match_test "IN_RANGE (INTVAL (op), 0, 12)")))
;; Match op = 0..15
(define_predicate "const_0_to_15_operand"

8
gcc/config/rs6000/rs6000.c
View File

@ -15839,9 +15839,9 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
if (arg1 == error_mark_node)
return expand_call (exp, target, false);
if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 11)
if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
{
error ("second argument to vec_vextract4b must 0..11");
error ("second argument to vec_vextract4b must 0..12");
return expand_call (exp, target, false);
}
break;
@ -15856,9 +15856,9 @@ altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
if (arg2 == error_mark_node)
return expand_call (exp, target, false);
if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 11)
if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
{
error ("third argument to vec_vinsert4b must 0..11");
error ("third argument to vec_vinsert4b must 0..12");
return expand_call (exp, target, false);
}
break;

4
gcc/config/rs6000/rs6000.md
View File

@ -855,7 +855,7 @@
lxsiwzx %x0,%y1
mtvsrwz %x0,%1
mfvsrwz %0,%x1
xxextractuw %x0,%x1,1"
xxextractuw %x0,%x1,4"
[(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")])
(define_insn_and_split "*zero_extendsi<mode>2_dot"
@ -5131,7 +5131,7 @@
lfiwzx %0,%y1
lxsiwzx %x0,%y1
mtvsrwz %x0,%1
xxextractuw %x0,%x1,1"
xxextractuw %x0,%x1,4"
[(set_attr "type" "fpload,fpload,mftgpr,vecexts")])
(define_insn_and_split "floatunssi<mode>2_lfiwzx"

12
gcc/config/rs6000/vsx.md
View File

@ -3813,7 +3813,7 @@
(define_expand "vextract4b"
[(set (match_operand:DI 0 "gpc_reg_operand")
(unspec:DI [(match_operand:V16QI 1 "vsx_register_operand")
(match_operand:QI 2 "const_0_to_11_operand")]
(match_operand:QI 2 "const_0_to_12_operand")]
UNSPEC_XXEXTRACTUW))]
"TARGET_P9_VECTOR"
{
@ -3824,7 +3824,7 @@
(define_insn_and_split "*vextract4b_internal"
[(set (match_operand:DI 0 "gpc_reg_operand" "=wj,r")
(unspec:DI [(match_operand:V16QI 1 "vsx_register_operand" "wa,v")
(match_operand:QI 2 "const_0_to_11_operand" "n,n")]
(match_operand:QI 2 "const_0_to_12_operand" "n,n")]
UNSPEC_XXEXTRACTUW))]
"TARGET_P9_VECTOR"
"@
@ -3852,7 +3852,7 @@
[(set (match_operand:V16QI 0 "vsx_register_operand")
(unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand")
(match_operand:V16QI 2 "vsx_register_operand")
(match_operand:QI 3 "const_0_to_11_operand")]
(match_operand:QI 3 "const_0_to_12_operand")]
UNSPEC_XXINSERTW))]
"TARGET_P9_VECTOR"
{
@ -3870,7 +3870,7 @@
[(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
(unspec:V16QI [(match_operand:V4SI 1 "vsx_register_operand" "wa")
(match_operand:V16QI 2 "vsx_register_operand" "0")
(match_operand:QI 3 "const_0_to_11_operand" "n")]
(match_operand:QI 3 "const_0_to_12_operand" "n")]
UNSPEC_XXINSERTW))]
"TARGET_P9_VECTOR"
"xxinsertw %x0,%x1,%3"
@ -3880,7 +3880,7 @@
[(set (match_operand:V16QI 0 "vsx_register_operand")
(unspec:V16QI [(match_operand:DI 1 "vsx_register_operand")
(match_operand:V16QI 2 "vsx_register_operand")
(match_operand:QI 3 "const_0_to_11_operand")]
(match_operand:QI 3 "const_0_to_12_operand")]
UNSPEC_XXINSERTW))]
"TARGET_P9_VECTOR"
{
@ -3892,7 +3892,7 @@
[(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
(unspec:V16QI [(match_operand:DI 1 "vsx_register_operand" "wj")
(match_operand:V16QI 2 "vsx_register_operand" "0")
(match_operand:QI 3 "const_0_to_11_operand" "n")]
(match_operand:QI 3 "const_0_to_12_operand" "n")]
UNSPEC_XXINSERTW))]
"TARGET_P9_VECTOR"
"xxinsertw %x0,%x1,%3"

5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2016-12-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-vinsert4b-2.c: Update test to test for 13
being out of bounds instead of 12.
2016-12-27 Uros Bizjak <ubizjak@gmail.com>
PR target/78904

4
gcc/testsuite/gcc.target/powerpc/p9-vinsert4b-2.c
View File

@ -8,7 +8,7 @@
vector signed char
ins_v4si (vector int vi, vector signed char vc)
{
return vec_vinsert4b (vi, vc, 12); /* { dg-error "vec_vinsert4b" } */
return vec_vinsert4b (vi, vc, 13); /* { dg-error "vec_vinsert4b" } */
}
vector unsigned char
@ -20,7 +20,7 @@ ins_di (long di, vector unsigned char vc, long n)
long
vext1 (vector signed char vc)
{
return vec_vextract4b (vc, 12); /* { dg-error "vec_vextract4b" } */
return vec_vextract4b (vc, 13); /* { dg-error "vec_vextract4b" } */
}
long