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re PR target/60839 (PowerPC: internal compiler error: in extract_insn, at recog.c:2154) 

2014-04-15  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/60839
	Revert following patch

	2014-04-02  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/60735
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
	software floating point or no floating point registers, do not
	allow any type in the FPRs.  Eliminate a test for SPE SIMD types
	in GPRs that occurs after we tested for GPRs that would never be
	true.

	* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
	Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
	since the FMOVE64 type is DFmode/DDmode.  If TARGET_E500_DOUBLE,
	specifically allow DDmode, since that does not use the SPE SIMD
	instructions.

From-SVN: r209425
This commit is contained in:
Bill Schmidt 2014-04-15 18:20:01 +00:00 committed by William Schmidt
parent 25dce5c6fb
commit dfe449d152
3 changed files with 26 additions and 6 deletions
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20
gcc/ChangeLog
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@ -1,3 +1,23 @@
2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/60839
Revert following patch
2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60735
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
software floating point or no floating point registers, do not
allow any type in the FPRs. Eliminate a test for SPE SIMD types
in GPRs that occurs after we tested for GPRs that would never be
true.
* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,
specifically allow DDmode, since that does not use the SPE SIMD
instructions.
2014-03-21 Mark Wielaard <mjw@redhat.com> 2014-03-21 Mark Wielaard <mjw@redhat.com>
* dwarf2out.c (gen_enumeration_type_die): Add DW_AT_const_value * dwarf2out.c (gen_enumeration_type_die): Add DW_AT_const_value

7
gcc/config/rs6000/rs6000.c
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@ -1752,9 +1752,6 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
modes and DImode. */ modes and DImode. */
if (FP_REGNO_P (regno)) if (FP_REGNO_P (regno))
{ {
if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
return 0;
if (SCALAR_FLOAT_MODE_P (mode) if (SCALAR_FLOAT_MODE_P (mode)
&& (mode != TDmode || (regno % 2) == 0) && (mode != TDmode || (regno % 2) == 0)
&& FP_REGNO_P (last_regno)) && FP_REGNO_P (last_regno))
@ -1783,6 +1780,10 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
|| mode == V1TImode); || mode == V1TImode);
/* ...but GPRs can hold SIMD data on the SPE in one register. */
if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
return 1;
/* We cannot put non-VSX TImode or PTImode anywhere except general register /* We cannot put non-VSX TImode or PTImode anywhere except general register
and it must be able to fit within the register set. */ and it must be able to fit within the register set. */

5
gcc/config/rs6000/rs6000.md
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@ -9394,9 +9394,8 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64 "! TARGET_POWERPC64
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
|| (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
&& (gpc_reg_operand (operands[0], <MODE>mode) && (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))" || gpc_reg_operand (operands[1], <MODE>mode))"
"#" "#"