mirror of git://gcc.gnu.org/git/gcc.git
i386: Add and use one_operand_p to vec_perm control struct.
* config/i386/i386.c (struct expand_vec_perm_d): Add one_operand_p. (ix86_expand_vector_init_duplicate): Initialize it. (expand_vec_perm_palignr): Likewise. (ix86_expand_vec_perm_const): Likewise. (ix86_vectorize_vec_perm_const_ok): Likewise. (expand_vec_perm_blend): Use it. (expand_vec_perm_vpermil): Likewise. (expand_vec_perm_pshufb): Likewise. (expand_vec_perm_1): Likewise. (expand_vec_perm_pshuflw_pshufhw): Likewise. (expand_vec_perm_interleave2): Likewise. (expand_vec_perm_vpermq_perm_1): Likewise. (expand_vec_perm_vperm2f128): Likewise. (expand_vec_perm_interleave3): Likewise. (expand_vec_perm_vperm2f128_vblend): Likewise. (expand_vec_perm_vpshufb2_vpermq): Likewise. (expand_vec_perm_vpshufb2_vpermq_even_odd): Likewise,. (expand_vec_perm_broadcast): Likewise. (expand_vec_perm_vpshufb4_vpermq2): Likewise. From-SVN: r186017
This commit is contained in:
Richard Henderson
Richard Henderson
parent
7b470faf61
commit
e025da0c31
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@ -1,3 +1,25 @@
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2012-03-30 Richard Henderson <rth@redhat.com>
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* config/i386/i386.c (struct expand_vec_perm_d): Add one_operand_p.
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(ix86_expand_vector_init_duplicate): Initialize it.
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(expand_vec_perm_palignr): Likewise.
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(ix86_expand_vec_perm_const): Likewise.
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(ix86_vectorize_vec_perm_const_ok): Likewise.
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(expand_vec_perm_blend): Use it.
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(expand_vec_perm_vpermil): Likewise.
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(expand_vec_perm_pshufb): Likewise.
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(expand_vec_perm_1): Likewise.
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(expand_vec_perm_pshuflw_pshufhw): Likewise.
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(expand_vec_perm_interleave2): Likewise.
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(expand_vec_perm_vpermq_perm_1): Likewise.
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(expand_vec_perm_vperm2f128): Likewise.
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(expand_vec_perm_interleave3): Likewise.
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(expand_vec_perm_vperm2f128_vblend): Likewise.
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(expand_vec_perm_vpshufb2_vpermq): Likewise.
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(expand_vec_perm_vpshufb2_vpermq_even_odd): Likewise,.
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(expand_vec_perm_broadcast): Likewise.
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(expand_vec_perm_vpshufb4_vpermq2): Likewise.
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2012-03-30 Richard Henderson <rth@redhat.com>
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* dwarf2out.c (gen_variable_die): Initialize off.
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@ -32938,6 +32938,7 @@ struct expand_vec_perm_d
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unsigned char perm[MAX_VECT_LEN];
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enum machine_mode vmode;
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unsigned char nelt;
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bool one_operand_p;
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bool testing_p;
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};
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@ -33038,6 +33039,7 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
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dperm.vmode = mode;
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dperm.nelt = GET_MODE_NUNITS (mode);
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dperm.op0 = dperm.op1 = gen_reg_rtx (mode);
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dperm.one_operand_p = true;
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/* Extend to SImode using a paradoxical SUBREG. */
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tmp1 = gen_reg_rtx (SImode);
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@ -35735,7 +35737,7 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d)
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rtx target, op0, op1, x;
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rtx rperm[32], vperm;
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if (d->op0 == d->op1)
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if (d->one_operand_p)
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return false;
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if (TARGET_AVX2 && GET_MODE_SIZE (vmode) == 32)
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;
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@ -35922,7 +35924,7 @@ expand_vec_perm_vpermil (struct expand_vec_perm_d *d)
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rtx rperm[8], vperm;
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unsigned i;
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if (!TARGET_AVX || d->vmode != V8SFmode || d->op0 != d->op1)
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if (!TARGET_AVX || d->vmode != V8SFmode || !d->one_operand_p)
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return false;
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/* We can only permute within the 128-bit lane. */
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@ -35998,7 +36000,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d)
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nelt = d->nelt;
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if (d->op0 != d->op1)
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if (!d->one_operand_p)
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{
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if (!TARGET_XOP || GET_MODE_SIZE (d->vmode) != 16)
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{
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@ -36086,7 +36088,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d)
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else
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{
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eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
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if (d->op0 != d->op1)
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if (!d->one_operand_p)
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mask = 2 * nelt - 1;
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else if (vmode == V16QImode)
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mask = nelt - 1;
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@ -36113,7 +36115,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d)
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target = gen_lowpart (vmode, d->target);
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op0 = gen_lowpart (vmode, d->op0);
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if (d->op0 == d->op1)
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if (d->one_operand_p)
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{
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if (vmode == V16QImode)
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emit_insn (gen_ssse3_pshufbv16qi3 (target, op0, vperm));
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@ -36145,7 +36147,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
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/* Check plain VEC_SELECT first, because AVX has instructions that could
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match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
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input where SEL+CONCAT may not. */
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if (d->op0 == d->op1)
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if (d->one_operand_p)
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{
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int mask = nelt - 1;
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bool identity_perm = true;
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@ -36242,7 +36244,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
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return true;
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/* Recognize interleave style patterns with reversed operands. */
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if (d->op0 != d->op1)
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if (!d->one_operand_p)
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{
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for (i = 0; i < nelt; ++i)
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{
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@ -36285,7 +36287,7 @@ expand_vec_perm_pshuflw_pshufhw (struct expand_vec_perm_d *d)
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unsigned i;
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bool ok;
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if (d->vmode != V8HImode || d->op0 != d->op1)
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if (d->vmode != V8HImode || !d->one_operand_p)
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return false;
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/* The two permutations only operate in 64-bit lanes. */
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@ -36357,6 +36359,7 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d)
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gen_lowpart (TImode, d->op0), shift));
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d->op0 = d->op1 = d->target;
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d->one_operand_p = true;
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in_order = true;
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for (i = 0; i < nelt; ++i)
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@ -36396,14 +36399,14 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d)
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if (GET_MODE_SIZE (d->vmode) == 16)
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{
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if (d->op0 == d->op1)
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if (d->one_operand_p)
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return false;
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}
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else if (GET_MODE_SIZE (d->vmode) == 32)
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{
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if (!TARGET_AVX)
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return false;
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/* For 32-byte modes allow even d->op0 == d->op1.
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/* For 32-byte modes allow even d->one_operand_p.
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The lack of cross-lane shuffling in some instructions
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might prevent a single insn shuffle. */
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dfinal = *d;
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@ -36528,11 +36531,11 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d)
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if (nzcnt == 1)
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{
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gcc_assert (d->op0 == d->op1);
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gcc_assert (d->one_operand_p);
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nonzero_halves[1] = nonzero_halves[0];
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same_halves = true;
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}
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else if (d->op0 == d->op1)
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else if (d->one_operand_p)
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{
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gcc_assert (nonzero_halves[0] == 0);
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gcc_assert (nonzero_halves[1] == 1);
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@ -36571,7 +36574,7 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d)
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}
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}
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}
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else if (d->op0 == d->op1)
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else if (d->one_operand_p)
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return false;
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else if (TARGET_AVX2
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&& (contents & (q[0] | q[2] | q[4] | q[6])) == contents)
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@ -36628,6 +36631,7 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d)
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}
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dfinal.op0 = gen_reg_rtx (dfinal.vmode);
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dfinal.op1 = dfinal.op0;
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dfinal.one_operand_p = true;
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dremap.target = dfinal.op0;
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/* Test if the final remap can be done with a single insn. For V4SFmode or
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@ -36671,7 +36675,7 @@ expand_vec_perm_vpermq_perm_1 (struct expand_vec_perm_d *d)
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if (!(TARGET_AVX2
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&& (d->vmode == V32QImode || d->vmode == V16HImode)
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&& d->op0 == d->op1))
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&& d->one_operand_p))
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return false;
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contents[0] = 0;
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@ -36699,6 +36703,7 @@ expand_vec_perm_vpermq_perm_1 (struct expand_vec_perm_d *d)
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dremap.target = gen_reg_rtx (V4DImode);
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dremap.op0 = gen_lowpart (V4DImode, d->op0);
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dremap.op1 = dremap.op0;
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dremap.one_operand_p = true;
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for (i = 0; i < 2; ++i)
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{
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unsigned int cnt = 0;
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@ -36712,6 +36717,7 @@ expand_vec_perm_vpermq_perm_1 (struct expand_vec_perm_d *d)
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dfinal = *d;
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dfinal.op0 = gen_lowpart (dfinal.vmode, dremap.target);
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dfinal.op1 = dfinal.op0;
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dfinal.one_operand_p = true;
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for (i = 0, j = 0; i < nelt; ++i)
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{
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if (i == nelt2)
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@ -36751,8 +36757,7 @@ expand_vec_perm_vperm2f128 (struct expand_vec_perm_d *d)
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return false;
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dsecond = *d;
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if (d->op0 == d->op1)
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dsecond.op1 = gen_reg_rtx (d->vmode);
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dsecond.one_operand_p = false;
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dsecond.testing_p = true;
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/* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
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@ -36821,10 +36826,7 @@ expand_vec_perm_vperm2f128 (struct expand_vec_perm_d *d)
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vperm2f128 on d->op0 and d->op1. */
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dsecond.testing_p = false;
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dfirst = *d;
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if (d->op0 == d->op1)
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dfirst.target = dsecond.op1;
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else
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dfirst.target = gen_reg_rtx (d->vmode);
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dfirst.target = gen_reg_rtx (d->vmode);
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for (i = 0; i < nelt; i++)
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dfirst.perm[i] = (i & (nelt2 - 1))
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+ ((perm >> (2 * (i >= nelt2))) & 3) * nelt2;
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@ -36845,9 +36847,8 @@ expand_vec_perm_vperm2f128 (struct expand_vec_perm_d *d)
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return true;
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}
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/* For d->op0 == d->op1 the only useful vperm2f128 permutation
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is 0x10. */
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if (d->op0 == d->op1)
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/* For one operand, the only useful vperm2f128 permutation is 0x10. */
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if (d->one_operand_p)
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return false;
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}
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@ -36864,7 +36865,7 @@ expand_vec_perm_interleave3 (struct expand_vec_perm_d *d)
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unsigned i, nelt;
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rtx (*gen) (rtx, rtx, rtx);
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if (d->op0 == d->op1)
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if (d->one_operand_p)
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return false;
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if (TARGET_AVX2 && GET_MODE_SIZE (d->vmode) == 32)
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;
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@ -36947,7 +36948,7 @@ expand_vec_perm_vperm2f128_vblend (struct expand_vec_perm_d *d)
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if (!TARGET_AVX
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|| TARGET_AVX2
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|| (d->vmode != V8SFmode && d->vmode != V4DFmode)
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|| d->op0 != d->op1)
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|| !d->one_operand_p)
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return false;
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dfirst = *d;
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@ -36985,6 +36986,7 @@ expand_vec_perm_vperm2f128_vblend (struct expand_vec_perm_d *d)
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dsecond = *d;
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dsecond.op0 = dfirst.target;
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dsecond.op1 = dfirst.target;
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dsecond.one_operand_p = true;
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dsecond.target = gen_reg_rtx (dsecond.vmode);
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for (i = 0; i < nelt; i++)
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dsecond.perm[i] = i ^ nelt2;
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@ -37009,7 +37011,7 @@ expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d)
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if (!TARGET_SSSE3 || GET_MODE_SIZE (d->vmode) != 16)
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return false;
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gcc_assert (d->op0 != d->op1);
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gcc_assert (!d->one_operand_p);
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nelt = d->nelt;
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eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode));
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@ -37064,7 +37066,7 @@ expand_vec_perm_vpshufb2_vpermq (struct expand_vec_perm_d *d)
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unsigned int i, nelt, eltsz;
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if (!TARGET_AVX2
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|| d->op0 != d->op1
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|| !d->one_operand_p
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|| (d->vmode != V32QImode && d->vmode != V16HImode))
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return false;
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@ -37132,7 +37134,7 @@ expand_vec_perm_vpshufb2_vpermq_even_odd (struct expand_vec_perm_d *d)
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unsigned int i, nelt, eltsz;
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if (!TARGET_AVX2
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|| d->op0 == d->op1
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|| d->one_operand_p
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|| (d->vmode != V32QImode && d->vmode != V16HImode))
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return false;
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@ -37491,7 +37493,7 @@ expand_vec_perm_broadcast (struct expand_vec_perm_d *d)
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{
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unsigned i, elt, nelt = d->nelt;
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if (d->op0 != d->op1)
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if (!d->one_operand_p)
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return false;
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elt = d->perm[0];
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@ -37514,7 +37516,7 @@ expand_vec_perm_vpshufb4_vpermq2 (struct expand_vec_perm_d *d)
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bool used[4];
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if (!TARGET_AVX2
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|| d->op0 == d->op1
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|| d->one_operand_p
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|| (d->vmode != V32QImode && d->vmode != V16HImode))
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return false;
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@ -37715,6 +37717,7 @@ ix86_expand_vec_perm_const (rtx operands[4])
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perm[i] = ei;
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}
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d.one_operand_p = true;
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switch (which)
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{
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default:
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@ -37722,51 +37725,39 @@ ix86_expand_vec_perm_const (rtx operands[4])
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case 3:
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if (!rtx_equal_p (d.op0, d.op1))
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break;
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{
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d.one_operand_p = false;
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break;
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}
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/* The elements of PERM do not suggest that only the first operand
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is used, but both operands are identical. Allow easier matching
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of the permutation by folding the permutation into the single
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input vector. */
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for (i = 0; i < nelt; ++i)
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if (d.perm[i] >= nelt)
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d.perm[i] -= nelt;
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/* FALLTHRU */
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case 1:
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d.op1 = d.op0;
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break;
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case 2:
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for (i = 0; i < nelt; ++i)
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d.perm[i] -= nelt;
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d.perm[i] &= nelt - 1;
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d.op0 = d.op1;
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break;
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case 1:
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d.op1 = d.op0;
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break;
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}
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if (ix86_expand_vec_perm_const_1 (&d))
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return true;
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/* If the mask says both arguments are needed, but they are the same,
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the above tried to expand with d.op0 == d.op1. If that didn't work,
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retry with d.op0 != d.op1 as that is what testing has been done with. */
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if (which == 3 && d.op0 == d.op1)
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/* If the selector says both arguments are needed, but the operands are the
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same, the above tried to expand with one_operand_p and flattened selector.
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If that didn't work, retry without one_operand_p; we succeeded with that
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during testing. */
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if (which == 3 && d.one_operand_p)
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{
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rtx seq;
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bool ok;
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d.one_operand_p = false;
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memcpy (d.perm, perm, sizeof (perm));
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d.op1 = gen_reg_rtx (d.vmode);
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start_sequence ();
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ok = ix86_expand_vec_perm_const_1 (&d);
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seq = get_insns ();
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end_sequence ();
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if (ok)
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{
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emit_move_insn (d.op1, d.op0);
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emit_insn (seq);
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return true;
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}
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return ix86_expand_vec_perm_const_1 (&d);
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}
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return false;
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@ -37780,7 +37771,7 @@ ix86_vectorize_vec_perm_const_ok (enum machine_mode vmode,
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{
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struct expand_vec_perm_d d;
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unsigned int i, nelt, which;
|
||||
bool ret, one_vec;
|
||||
bool ret;
|
||||
|
||||
d.vmode = vmode;
|
||||
d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
|
||||
|
|
@ -37817,17 +37808,17 @@ ix86_vectorize_vec_perm_const_ok (enum machine_mode vmode,
|
|||
d.perm[i] -= nelt;
|
||||
|
||||
/* Check whether the mask can be applied to the vector type. */
|
||||
one_vec = (which != 3);
|
||||
d.one_operand_p = (which != 3);
|
||||
|
||||
/* Implementable with shufps or pshufd. */
|
||||
if (one_vec && (d.vmode == V4SFmode || d.vmode == V4SImode))
|
||||
if (d.one_operand_p && (d.vmode == V4SFmode || d.vmode == V4SImode))
|
||||
return true;
|
||||
|
||||
/* Otherwise we have to go through the motions and see if we can
|
||||
figure out how to generate the requested permutation. */
|
||||
d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
|
||||
d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
|
||||
if (!one_vec)
|
||||
if (!d.one_operand_p)
|
||||
d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
|
||||
|
||||
start_sequence ();
|
||||
|
|
@ -37848,6 +37839,7 @@ ix86_expand_vec_extract_even_odd (rtx targ, rtx op0, rtx op1, unsigned odd)
|
|||
d.op1 = op1;
|
||||
d.vmode = GET_MODE (targ);
|
||||
d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
|
||||
d.one_operand_p = false;
|
||||
d.testing_p = false;
|
||||
|
||||
for (i = 0; i < nelt; ++i)
|
||||
|
|
|
|||
Loading…
Reference in New Issue