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rs6000: Remove TARGET_SPE and TARGET_SPE_ABI and friends 

* config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
	SPE ABI handling.
	* config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2.
	(paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3,
	paired_divv2sf3): Similar.
	* config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI,
	SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify.
	* config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and
	RS6000_BUILTIN_S.
	Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X.
	Rename the paired_* instruction patterns.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not
	define __SPE__.
	* config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete.
	* config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S.
	(struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size,
	spe_padding_size, and spe_64bit_regs_used.  Replace TARGET_SPE and
	TARGET_SPE_ABI with 0, simplify.  Replace SPE_VECTOR_MODE with
	PAIRED_VECTOR_MODE.
	(struct machine_function): Delete field spe_insn_chain_scanned_p.
	(spe_func_has_64bit_regs_p): Delete.
	(spe_expand_predicate_builtin): Delete.
	(spe_expand_evsel_builtin): Delete.
	(TARGET_DWARF_REGISTER_SPAN): Do not define.
	(TARGET_MEMBER_TYPE_FORCES_BLK): Do not define.
	(invalid_e500_subreg): Delete.
	(rs6000_legitimize_address): Always force_reg op2 as well, for
	paired single memory accesses.
	(rs6000_member_type_forces_blk): Delete.
	(rs6000_spe_function_arg): Delete.
	(rs6000_expand_unop_builtin): Delete SPE handling.
	(rs6000_expand_binop_builtin): Ditto.
	(spe_expand_stv_builtin): Delete.
	(bdesc_2arg_spe): Delete.
	(spe_expand_builtin): Delete.
	(spe_expand_predicate_builtin): Delete.
	(spe_expand_evsel_builtin): Delete.
	(rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling.
	(spe_init_builtins): Delete.
	(spe_func_has_64bit_regs_p): Delete.
	(savres_routine_name): Delete "info" parameter.  Adjust callers.
	(rs6000_emit_stack_reset): Ditto.
	(rs6000_dwarf_register_span): Delete.
	* config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE,
	UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P,
	SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S):
	Delete.
	* config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO):
	Delete.
	* config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete.
	* config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE.
	* config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3,
	mulv2sf3, divv2sf3): Delete expanders.

From-SVN: r248980
This commit is contained in:
Segher Boessenkool 2017-06-07 17:22:33 +02:00 committed by Segher Boessenkool
parent beaca945bb
commit e075a6ccbf
13 changed files with 123 additions and 4654 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
gcc/ChangeLog
View File

@ -1,3 +1,59 @@
2017-06-07 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
SPE ABI handling.
* config/rs6000/paired.md (paired_negv2sf2): Rename to negv2sf2.
(paired_absv2sf2, paired_addv2sf3, paired_subv2sf3, paired_mulv2sf3,
paired_divv2sf3): Similar.
* config/rs6000/predicates.md: Replace TARGET_SPE, TARGET_SPE_ABI,
SPE_VECTOR_MODE and SPE_HIGH_REGNO_P by 0; simplify.
* config/rs6000/rs6000-builtin.def: Delete RS6000_BUILTIN_E and
RS6000_BUILTIN_S.
Delete BU_SPE_1, BU_SPE_2, BU_SPE_3, BU_SPE_E, BU_SPE_P, and BU_SPE_X.
Rename the paired_* instruction patterns.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Do not
define __SPE__.
* config/rs6000/rs6000-protos.h (invalid_e500_subreg): Delete.
* config/rs6000/rs6000.c: Delete RS6000_BUILTIN_E and RS6000_BUILTIN_S.
(struct rs6000_stack): Delete fields spe_gp_save_offset, spe_gp_size,
spe_padding_size, and spe_64bit_regs_used. Replace TARGET_SPE and
TARGET_SPE_ABI with 0, simplify. Replace SPE_VECTOR_MODE with
PAIRED_VECTOR_MODE.
(struct machine_function): Delete field spe_insn_chain_scanned_p.
(spe_func_has_64bit_regs_p): Delete.
(spe_expand_predicate_builtin): Delete.
(spe_expand_evsel_builtin): Delete.
(TARGET_DWARF_REGISTER_SPAN): Do not define.
(TARGET_MEMBER_TYPE_FORCES_BLK): Do not define.
(invalid_e500_subreg): Delete.
(rs6000_legitimize_address): Always force_reg op2 as well, for
paired single memory accesses.
(rs6000_member_type_forces_blk): Delete.
(rs6000_spe_function_arg): Delete.
(rs6000_expand_unop_builtin): Delete SPE handling.
(rs6000_expand_binop_builtin): Ditto.
(spe_expand_stv_builtin): Delete.
(bdesc_2arg_spe): Delete.
(spe_expand_builtin): Delete.
(spe_expand_predicate_builtin): Delete.
(spe_expand_evsel_builtin): Delete.
(rs6000_invalid_builtin): Remove RS6000_BTM_SPE handling.
(spe_init_builtins): Delete.
(spe_func_has_64bit_regs_p): Delete.
(savres_routine_name): Delete "info" parameter. Adjust callers.
(rs6000_emit_stack_reset): Ditto.
(rs6000_dwarf_register_span): Delete.
* config/rs6000/rs6000.h (TARGET_SPE_ABI, TARGET_SPE,
UNITS_PER_SPE_WORD, SPE_HIGH_REGNO_P, SPE_SIMD_REGNO_P,
SPE_VECTOR_MODE, RS6000_BTM_SPE, RS6000_BUILTIN_E, RS6000_BUILTIN_S):
Delete.
* config/rs6000/rs6000.md (FIRST_SPE_HIGH_REGNO, LAST_SPE_HIGH_REGNO):
Delete.
* config/rs6000/rs6000.opt (-mabi=spe, -mabi=no-spe): Delete.
* config/rs6000/spe.md: Delete every pattern that uses TARGET_SPE.
* config/rs6000/vector.md (absv2sf2, negv2sf2, addv2sf3, subv2sf3,
mulv2sf3, divv2sf3): Delete expanders.
2017-06-07 Segher Boessenkool <segher@kernel.crashing.org>
config/rs6000/rs6000.md (UNSPEC_MV_CR_GT): Delete.

9
gcc/common/config/rs6000/rs6000-common.c
View File

@ -207,15 +207,6 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
break;
#endif
case OPT_mabi_altivec:
/* Enabling the AltiVec ABI turns off the SPE ABI. */
opts->x_rs6000_spe_abi = 0;
break;
case OPT_mabi_spe:
opts->x_rs6000_altivec_abi = 0;
break;
case OPT_mlong_double_:
if (value != 64 && value != 128)
{

12
gcc/config/rs6000/paired.md
View File

@ -26,7 +26,7 @@
UNSPEC_EXTODD_V2SF
])
(define_insn "paired_negv2sf2"
(define_insn "negv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
@ -40,7 +40,7 @@
"ps_rsqrte %0,%1"
[(set_attr "type" "fp")])
(define_insn "paired_absv2sf2"
(define_insn "absv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
"TARGET_PAIRED_FLOAT"
@ -54,7 +54,7 @@
"ps_nabs %0,%1"
[(set_attr "type" "fp")])
(define_insn "paired_addv2sf3"
(define_insn "addv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@ -62,7 +62,7 @@
"ps_add %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "paired_subv2sf3"
(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@ -70,7 +70,7 @@
"ps_sub %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "paired_mulv2sf3"
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]
@ -85,7 +85,7 @@
"ps_res %0,%1"
[(set_attr "type" "fp")])
(define_insn "paired_divv2sf3"
(define_insn "divv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
(match_operand:V2SF 2 "gpc_reg_operand" "f")))]

49
gcc/config/rs6000/predicates.md
View File

@ -299,9 +299,6 @@
(define_predicate "gpc_reg_operand"
(match_operand 0 "register_operand")
{
if (TARGET_SPE && invalid_e500_subreg (op, mode))
return 0;
if (GET_CODE (op) == SUBREG)
{
if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
@ -331,9 +328,6 @@
(define_predicate "int_reg_operand"
(match_operand 0 "register_operand")
{
if (TARGET_SPE && invalid_e500_subreg (op, mode))
return 0;
if (GET_CODE (op) == SUBREG)
{
if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
@ -357,9 +351,6 @@
(define_predicate "int_reg_operand_not_pseudo"
(match_operand 0 "register_operand")
{
if (TARGET_SPE && invalid_e500_subreg (op, mode))
return 0;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
@ -711,32 +702,6 @@
return easy_altivec_constant (op, mode);
}
if (SPE_VECTOR_MODE (mode))
{
int cst, cst2;
if (zero_constant (op, mode))
return true;
if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
return false;
/* Limit SPE vectors to 15 bits signed. These we can generate with:
li r0, CONSTANT1
evmergelo r0, r0, r0
li r0, CONSTANT2
I don't know how efficient it would be to allow bigger constants,
considering we'll have an extra 'ori' for every 'li'. I doubt 5
instructions is better than a 64-bit memory load, but I don't
have the e500 timing specs. */
if (mode == V2SImode)
{
cst = INTVAL (CONST_VECTOR_ELT (op, 0));
cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
return cst >= -0x7fff && cst <= 0x7fff
&& cst2 >= -0x7fff && cst2 <= 0x7fff;
}
}
return false;
})
@ -1135,12 +1100,6 @@
&& easy_vector_constant (op, mode))
return 1;
/* Do not allow invalid E500 subregs. */
if (TARGET_SPE
&& GET_CODE (op) == SUBREG
&& invalid_e500_subreg (op, mode))
return 0;
/* For floating-point or multi-word mode, the only remaining valid type
is a register. */
if (SCALAR_FLOAT_MODE_P (mode)
@ -1199,16 +1158,10 @@
return gpc_reg_operand (op, mode);
})
;; Return true if OP is a non-immediate operand and not an invalid
;; SUBREG operation on the e500.
;; Return true if OP is a non-immediate operand.
(define_predicate "rs6000_nonimmediate_operand"
(match_code "reg,subreg,mem")
{
if (TARGET_SPE
&& GET_CODE (op) == SUBREG
&& invalid_e500_subreg (op, mode))
return 0;
return nonimmediate_operand (op, mode);
})

313
gcc/config/rs6000/rs6000-builtin.def
View File

@ -30,11 +30,9 @@
RS6000_BUILTIN_3 -- 3 arg builtins
RS6000_BUILTIN_A -- ABS builtins
RS6000_BUILTIN_D -- DST builtins
RS6000_BUILTIN_E -- SPE EVSEL builtins.
RS6000_BUILTIN_H -- HTM builtins
RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins
RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins
RS6000_BUILTIN_S -- SPE predicate builtins
RS6000_BUILTIN_X -- special builtins
Each of the above macros takes 4 arguments:
@ -68,10 +66,6 @@
#error "RS6000_BUILTIN_D is not defined."
#endif
#ifndef RS6000_BUILTIN_E
#error "RS6000_BUILTIN_E is not defined."
#endif
#ifndef RS6000_BUILTIN_H
#error "RS6000_BUILTIN_H is not defined."
#endif
@ -84,10 +78,6 @@
#error "RS6000_BUILTIN_Q is not defined."
#endif
#ifndef RS6000_BUILTIN_S
#error "RS6000_BUILTIN_S is not defined."
#endif
#ifndef RS6000_BUILTIN_X
#error "RS6000_BUILTIN_X is not defined."
#endif
@ -551,55 +541,6 @@
| RS6000_BTC_VOID), \
CODE_FOR_ ## ICODE) /* ICODE */
/* SPE convenience macros. */
#define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_spe_" NAME, /* NAME */ \
RS6000_BTM_SPE, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_SPE_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_spe_" NAME, /* NAME */ \
RS6000_BTM_SPE, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_SPE_3(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_3 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_spe_" NAME, /* NAME */ \
RS6000_BTM_SPE, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_SPE_E(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_E (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_spe_" NAME, /* NAME */ \
RS6000_BTM_SPE, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_EVSEL), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_SPE_P(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_S (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_spe_" NAME, /* NAME */ \
RS6000_BTM_SPE, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_PREDICATE), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_SPE_X(ENUM, NAME, ATTR) \
RS6000_BUILTIN_X (SPE_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_spe_" NAME, /* NAME */ \
RS6000_BTM_SPE, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_nothing) /* ICODE */
/* Paired floating point convenience macros. */
#define BU_PAIRED_1(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_1 (PAIRED_BUILTIN_ ## ENUM, /* ENUM */ \
@ -2370,10 +2311,10 @@ BU_PAIRED_3 (SUM1, "sum1", FP, paired_sum1)
BU_PAIRED_3 (SELV2SF4, "selv2sf4", CONST, selv2sf4)
/* 2 argument paired floating point builtins. */
BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, paired_divv2sf3)
BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, paired_addv2sf3)
BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, paired_subv2sf3)
BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, paired_mulv2sf3)
BU_PAIRED_2 (DIVV2SF3, "divv2sf3", FP, divv2sf3)
BU_PAIRED_2 (ADDV2SF3, "addv2sf3", FP, addv2sf3)
BU_PAIRED_2 (SUBV2SF3, "subv2sf3", FP, subv2sf3)
BU_PAIRED_2 (MULV2SF3, "mulv2sf3", FP, mulv2sf3)
BU_PAIRED_2 (MULS0, "muls0", FP, paired_muls0)
BU_PAIRED_2 (MULS1, "muls1", FP, paired_muls1)
BU_PAIRED_2 (MERGE00, "merge00", CONST, paired_merge00)
@ -2382,9 +2323,9 @@ BU_PAIRED_2 (MERGE10, "merge10", CONST, paired_merge10)
BU_PAIRED_2 (MERGE11, "merge11", CONST, paired_merge11)
/* 1 argument paired floating point builtin functions. */
BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, paired_absv2sf2)
BU_PAIRED_1 (ABSV2SF2, "absv2sf2", CONST, absv2sf2)
BU_PAIRED_1 (NABSV2SF2, "nabsv2sf2", CONST, nabsv2sf2)
BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, paired_negv2sf2)
BU_PAIRED_1 (NEGV2SF2, "negv2sf2", CONST, negv2sf2)
BU_PAIRED_1 (SQRTV2SF2, "sqrtv2sf2", FP, sqrtv2sf2)
BU_PAIRED_1 (RESV2SF, "resv2sf2", FP, resv2sf2)
@ -2395,248 +2336,6 @@ BU_PAIRED_X (LX, "lx", MISC)
/* Paired predicates. */
BU_PAIRED_P (CMPU0, "cmpu0", CONST, paired_cmpu0)
BU_PAIRED_P (CMPU1, "cmpu1", CONST, paired_cmpu1)
/* PowerPC E500 builtins (SPE). */
BU_SPE_2 (EVADDW, "evaddw", MISC, addv2si3)
BU_SPE_2 (EVAND, "evand", MISC, andv2si3)
BU_SPE_2 (EVANDC, "evandc", MISC, spe_evandc)
BU_SPE_2 (EVDIVWS, "evdivws", MISC, divv2si3)
BU_SPE_2 (EVDIVWU, "evdivwu", MISC, spe_evdivwu)
BU_SPE_2 (EVEQV, "eveqv", MISC, spe_eveqv)
BU_SPE_2 (EVFSADD, "evfsadd", MISC, spe_evfsadd)
BU_SPE_2 (EVFSDIV, "evfsdiv", MISC, spe_evfsdiv)
BU_SPE_2 (EVFSMUL, "evfsmul", MISC, spe_evfsmul)
BU_SPE_2 (EVFSSUB, "evfssub", MISC, spe_evfssub)
BU_SPE_2 (EVMERGEHI, "evmergehi", MISC, spe_evmergehi)
BU_SPE_2 (EVMERGEHILO, "evmergehilo", MISC, spe_evmergehilo)
BU_SPE_2 (EVMERGELO, "evmergelo", MISC, spe_evmergelo)
BU_SPE_2 (EVMERGELOHI, "evmergelohi", MISC, spe_evmergelohi)
BU_SPE_2 (EVMHEGSMFAA, "evmhegsmfaa", MISC, spe_evmhegsmfaa)
BU_SPE_2 (EVMHEGSMFAN, "evmhegsmfan", MISC, spe_evmhegsmfan)
BU_SPE_2 (EVMHEGSMIAA, "evmhegsmiaa", MISC, spe_evmhegsmiaa)
BU_SPE_2 (EVMHEGSMIAN, "evmhegsmian", MISC, spe_evmhegsmian)
BU_SPE_2 (EVMHEGUMIAA, "evmhegumiaa", MISC, spe_evmhegumiaa)
BU_SPE_2 (EVMHEGUMIAN, "evmhegumian", MISC, spe_evmhegumian)
BU_SPE_2 (EVMHESMF, "evmhesmf", MISC, spe_evmhesmf)
BU_SPE_2 (EVMHESMFA, "evmhesmfa", MISC, spe_evmhesmfa)
BU_SPE_2 (EVMHESMFAAW, "evmhesmfaaw", MISC, spe_evmhesmfaaw)
BU_SPE_2 (EVMHESMFANW, "evmhesmfanw", MISC, spe_evmhesmfanw)
BU_SPE_2 (EVMHESMI, "evmhesmi", MISC, spe_evmhesmi)
BU_SPE_2 (EVMHESMIA, "evmhesmia", MISC, spe_evmhesmia)
BU_SPE_2 (EVMHESMIAAW, "evmhesmiaaw", MISC, spe_evmhesmiaaw)
BU_SPE_2 (EVMHESMIANW, "evmhesmianw", MISC, spe_evmhesmianw)
BU_SPE_2 (EVMHESSF, "evmhessf", MISC, spe_evmhessf)
BU_SPE_2 (EVMHESSFA, "evmhessfa", MISC, spe_evmhessfa)
BU_SPE_2 (EVMHESSFAAW, "evmhessfaaw", MISC, spe_evmhessfaaw)
BU_SPE_2 (EVMHESSFANW, "evmhessfanw", MISC, spe_evmhessfanw)
BU_SPE_2 (EVMHESSIAAW, "evmhessiaaw", MISC, spe_evmhessiaaw)
BU_SPE_2 (EVMHESSIANW, "evmhessianw", MISC, spe_evmhessianw)
BU_SPE_2 (EVMHEUMI, "evmheumi", MISC, spe_evmheumi)
BU_SPE_2 (EVMHEUMIA, "evmheumia", MISC, spe_evmheumia)
BU_SPE_2 (EVMHEUMIAAW, "evmheumiaaw", MISC, spe_evmheumiaaw)
BU_SPE_2 (EVMHEUMIANW, "evmheumianw", MISC, spe_evmheumianw)
BU_SPE_2 (EVMHEUSIAAW, "evmheusiaaw", MISC, spe_evmheusiaaw)
BU_SPE_2 (EVMHEUSIANW, "evmheusianw", MISC, spe_evmheusianw)
BU_SPE_2 (EVMHOGSMFAA, "evmhogsmfaa", MISC, spe_evmhogsmfaa)
BU_SPE_2 (EVMHOGSMFAN, "evmhogsmfan", MISC, spe_evmhogsmfan)
BU_SPE_2 (EVMHOGSMIAA, "evmhogsmiaa", MISC, spe_evmhogsmiaa)
BU_SPE_2 (EVMHOGSMIAN, "evmhogsmian", MISC, spe_evmhogsmian)
BU_SPE_2 (EVMHOGUMIAA, "evmhogumiaa", MISC, spe_evmhogumiaa)
BU_SPE_2 (EVMHOGUMIAN, "evmhogumian", MISC, spe_evmhogumian)
BU_SPE_2 (EVMHOSMF, "evmhosmf", MISC, spe_evmhosmf)
BU_SPE_2 (EVMHOSMFA, "evmhosmfa", MISC, spe_evmhosmfa)
BU_SPE_2 (EVMHOSMFAAW, "evmhosmfaaw", MISC, spe_evmhosmfaaw)
BU_SPE_2 (EVMHOSMFANW, "evmhosmfanw", MISC, spe_evmhosmfanw)
BU_SPE_2 (EVMHOSMI, "evmhosmi", MISC, spe_evmhosmi)
BU_SPE_2 (EVMHOSMIA, "evmhosmia", MISC, spe_evmhosmia)
BU_SPE_2 (EVMHOSMIAAW, "evmhosmiaaw", MISC, spe_evmhosmiaaw)
BU_SPE_2 (EVMHOSMIANW, "evmhosmianw", MISC, spe_evmhosmianw)
BU_SPE_2 (EVMHOSSF, "evmhossf", MISC, spe_evmhossf)
BU_SPE_2 (EVMHOSSFA, "evmhossfa", MISC, spe_evmhossfa)
BU_SPE_2 (EVMHOSSFAAW, "evmhossfaaw", MISC, spe_evmhossfaaw)
BU_SPE_2 (EVMHOSSFANW, "evmhossfanw", MISC, spe_evmhossfanw)
BU_SPE_2 (EVMHOSSIAAW, "evmhossiaaw", MISC, spe_evmhossiaaw)
BU_SPE_2 (EVMHOSSIANW, "evmhossianw", MISC, spe_evmhossianw)
BU_SPE_2 (EVMHOUMI, "evmhoumi", MISC, spe_evmhoumi)
BU_SPE_2 (EVMHOUMIA, "evmhoumia", MISC, spe_evmhoumia)
BU_SPE_2 (EVMHOUMIAAW, "evmhoumiaaw", MISC, spe_evmhoumiaaw)
BU_SPE_2 (EVMHOUMIANW, "evmhoumianw", MISC, spe_evmhoumianw)
BU_SPE_2 (EVMHOUSIAAW, "evmhousiaaw", MISC, spe_evmhousiaaw)
BU_SPE_2 (EVMHOUSIANW, "evmhousianw", MISC, spe_evmhousianw)
BU_SPE_2 (EVMWHSMF, "evmwhsmf", MISC, spe_evmwhsmf)
BU_SPE_2 (EVMWHSMFA, "evmwhsmfa", MISC, spe_evmwhsmfa)
BU_SPE_2 (EVMWHSMI, "evmwhsmi", MISC, spe_evmwhsmi)
BU_SPE_2 (EVMWHSMIA, "evmwhsmia", MISC, spe_evmwhsmia)
BU_SPE_2 (EVMWHSSF, "evmwhssf", MISC, spe_evmwhssf)
BU_SPE_2 (EVMWHSSFA, "evmwhssfa", MISC, spe_evmwhssfa)
BU_SPE_2 (EVMWHUMI, "evmwhumi", MISC, spe_evmwhumi)
BU_SPE_2 (EVMWHUMIA, "evmwhumia", MISC, spe_evmwhumia)
BU_SPE_2 (EVMWLSMIAAW, "evmwlsmiaaw", MISC, spe_evmwlsmiaaw)
BU_SPE_2 (EVMWLSMIANW, "evmwlsmianw", MISC, spe_evmwlsmianw)
BU_SPE_2 (EVMWLSSIAAW, "evmwlssiaaw", MISC, spe_evmwlssiaaw)
BU_SPE_2 (EVMWLSSIANW, "evmwlssianw", MISC, spe_evmwlssianw)
BU_SPE_2 (EVMWLUMI, "evmwlumi", MISC, spe_evmwlumi)
BU_SPE_2 (EVMWLUMIA, "evmwlumia", MISC, spe_evmwlumia)
BU_SPE_2 (EVMWLUMIAAW, "evmwlumiaaw", MISC, spe_evmwlumiaaw)
BU_SPE_2 (EVMWLUMIANW, "evmwlumianw", MISC, spe_evmwlumianw)
BU_SPE_2 (EVMWLUSIAAW, "evmwlusiaaw", MISC, spe_evmwlusiaaw)
BU_SPE_2 (EVMWLUSIANW, "evmwlusianw", MISC, spe_evmwlusianw)
BU_SPE_2 (EVMWSMF, "evmwsmf", MISC, spe_evmwsmf)
BU_SPE_2 (EVMWSMFA, "evmwsmfa", MISC, spe_evmwsmfa)
BU_SPE_2 (EVMWSMFAA, "evmwsmfaa", MISC, spe_evmwsmfaa)
BU_SPE_2 (EVMWSMFAN, "evmwsmfan", MISC, spe_evmwsmfan)
BU_SPE_2 (EVMWSMI, "evmwsmi", MISC, spe_evmwsmi)
BU_SPE_2 (EVMWSMIA, "evmwsmia", MISC, spe_evmwsmia)
BU_SPE_2 (EVMWSMIAA, "evmwsmiaa", MISC, spe_evmwsmiaa)
BU_SPE_2 (EVMWSMIAN, "evmwsmian", MISC, spe_evmwsmian)
BU_SPE_2 (EVMWSSF, "evmwssf", MISC, spe_evmwssf)
BU_SPE_2 (EVMWSSFA, "evmwssfa", MISC, spe_evmwssfa)
BU_SPE_2 (EVMWSSFAA, "evmwssfaa", MISC, spe_evmwssfaa)
BU_SPE_2 (EVMWSSFAN, "evmwssfan", MISC, spe_evmwssfan)
BU_SPE_2 (EVMWUMI, "evmwumi", MISC, spe_evmwumi)
BU_SPE_2 (EVMWUMIA, "evmwumia", MISC, spe_evmwumia)
BU_SPE_2 (EVMWUMIAA, "evmwumiaa", MISC, spe_evmwumiaa)
BU_SPE_2 (EVMWUMIAN, "evmwumian", MISC, spe_evmwumian)
BU_SPE_2 (EVNAND, "evnand", MISC, spe_evnand)
BU_SPE_2 (EVNOR, "evnor", MISC, spe_evnor)
BU_SPE_2 (EVOR, "evor", MISC, spe_evor)
BU_SPE_2 (EVORC, "evorc", MISC, spe_evorc)
BU_SPE_2 (EVRLW, "evrlw", MISC, spe_evrlw)
BU_SPE_2 (EVSLW, "evslw", MISC, spe_evslw)
BU_SPE_2 (EVSRWS, "evsrws", MISC, spe_evsrws)
BU_SPE_2 (EVSRWU, "evsrwu", MISC, spe_evsrwu)
BU_SPE_2 (EVSUBFW, "evsubfw", MISC, subv2si3)
/* SPE binary operations expecting a 5-bit unsigned literal. */
BU_SPE_2 (EVADDIW, "evaddiw", MISC, spe_evaddiw)
BU_SPE_2 (EVRLWI, "evrlwi", MISC, spe_evrlwi)
BU_SPE_2 (EVSLWI, "evslwi", MISC, spe_evslwi)
BU_SPE_2 (EVSRWIS, "evsrwis", MISC, spe_evsrwis)
BU_SPE_2 (EVSRWIU, "evsrwiu", MISC, spe_evsrwiu)
BU_SPE_2 (EVSUBIFW, "evsubifw", MISC, spe_evsubifw)
BU_SPE_2 (EVMWHSSFAA, "evmwhssfaa", MISC, spe_evmwhssfaa)
BU_SPE_2 (EVMWHSSMAA, "evmwhssmaa", MISC, spe_evmwhssmaa)
BU_SPE_2 (EVMWHSMFAA, "evmwhsmfaa", MISC, spe_evmwhsmfaa)
BU_SPE_2 (EVMWHSMIAA, "evmwhsmiaa", MISC, spe_evmwhsmiaa)
BU_SPE_2 (EVMWHUSIAA, "evmwhusiaa", MISC, spe_evmwhusiaa)
BU_SPE_2 (EVMWHUMIAA, "evmwhumiaa", MISC, spe_evmwhumiaa)
BU_SPE_2 (EVMWHSSFAN, "evmwhssfan", MISC, spe_evmwhssfan)
BU_SPE_2 (EVMWHSSIAN, "evmwhssian", MISC, spe_evmwhssian)
BU_SPE_2 (EVMWHSMFAN, "evmwhsmfan", MISC, spe_evmwhsmfan)
BU_SPE_2 (EVMWHSMIAN, "evmwhsmian", MISC, spe_evmwhsmian)
BU_SPE_2 (EVMWHUSIAN, "evmwhusian", MISC, spe_evmwhusian)
BU_SPE_2 (EVMWHUMIAN, "evmwhumian", MISC, spe_evmwhumian)
BU_SPE_2 (EVMWHGSSFAA, "evmwhgssfaa", MISC, spe_evmwhgssfaa)
BU_SPE_2 (EVMWHGSMFAA, "evmwhgsmfaa", MISC, spe_evmwhgsmfaa)
BU_SPE_2 (EVMWHGSMIAA, "evmwhgsmiaa", MISC, spe_evmwhgsmiaa)
BU_SPE_2 (EVMWHGUMIAA, "evmwhgumiaa", MISC, spe_evmwhgumiaa)
BU_SPE_2 (EVMWHGSSFAN, "evmwhgssfan", MISC, spe_evmwhgssfan)
BU_SPE_2 (EVMWHGSMFAN, "evmwhgsmfan", MISC, spe_evmwhgsmfan)
BU_SPE_2 (EVMWHGSMIAN, "evmwhgsmian", MISC, spe_evmwhgsmian)
BU_SPE_2 (EVMWHGUMIAN, "evmwhgumian", MISC, spe_evmwhgumian)
BU_SPE_2 (BRINC, "brinc", MISC, spe_brinc)
BU_SPE_2 (EVXOR, "evxor", MISC, xorv2si3)
/* SPE predicate builtins. */
BU_SPE_P (EVCMPEQ, "evcmpeq", MISC, spe_evcmpeq)
BU_SPE_P (EVCMPGTS, "evcmpgts", MISC, spe_evcmpgts)
BU_SPE_P (EVCMPGTU, "evcmpgtu", MISC, spe_evcmpgtu)
BU_SPE_P (EVCMPLTS, "evcmplts", MISC, spe_evcmplts)
BU_SPE_P (EVCMPLTU, "evcmpltu", MISC, spe_evcmpltu)
BU_SPE_P (EVFSCMPEQ, "evfscmpeq", MISC, spe_evfscmpeq)
BU_SPE_P (EVFSCMPGT, "evfscmpgt", MISC, spe_evfscmpgt)
BU_SPE_P (EVFSCMPLT, "evfscmplt", MISC, spe_evfscmplt)
BU_SPE_P (EVFSTSTEQ, "evfststeq", MISC, spe_evfststeq)
BU_SPE_P (EVFSTSTGT, "evfststgt", MISC, spe_evfststgt)
BU_SPE_P (EVFSTSTLT, "evfststlt", MISC, spe_evfststlt)
/* SPE evsel builtins. */
BU_SPE_E (EVSEL_CMPGTS, "evsel_gts", MISC, spe_evcmpgts)
BU_SPE_E (EVSEL_CMPGTU, "evsel_gtu", MISC, spe_evcmpgtu)
BU_SPE_E (EVSEL_CMPLTS, "evsel_lts", MISC, spe_evcmplts)
BU_SPE_E (EVSEL_CMPLTU, "evsel_ltu", MISC, spe_evcmpltu)
BU_SPE_E (EVSEL_CMPEQ, "evsel_eq", MISC, spe_evcmpeq)
BU_SPE_E (EVSEL_FSCMPGT, "evsel_fsgt", MISC, spe_evfscmpgt)
BU_SPE_E (EVSEL_FSCMPLT, "evsel_fslt", MISC, spe_evfscmplt)
BU_SPE_E (EVSEL_FSCMPEQ, "evsel_fseq", MISC, spe_evfscmpeq)
BU_SPE_E (EVSEL_FSTSTGT, "evsel_fststgt", MISC, spe_evfststgt)
BU_SPE_E (EVSEL_FSTSTLT, "evsel_fststlt", MISC, spe_evfststlt)
BU_SPE_E (EVSEL_FSTSTEQ, "evsel_fststeq", MISC, spe_evfststeq)
BU_SPE_1 (EVABS, "evabs", CONST, absv2si2)
BU_SPE_1 (EVADDSMIAAW, "evaddsmiaaw", CONST, spe_evaddsmiaaw)
BU_SPE_1 (EVADDSSIAAW, "evaddssiaaw", CONST, spe_evaddssiaaw)
BU_SPE_1 (EVADDUMIAAW, "evaddumiaaw", CONST, spe_evaddumiaaw)
BU_SPE_1 (EVADDUSIAAW, "evaddusiaaw", CONST, spe_evaddusiaaw)
BU_SPE_1 (EVCNTLSW, "evcntlsw", CONST, spe_evcntlsw)
BU_SPE_1 (EVCNTLZW, "evcntlzw", CONST, spe_evcntlzw)
BU_SPE_1 (EVEXTSB, "evextsb", CONST, spe_evextsb)
BU_SPE_1 (EVEXTSH, "evextsh", CONST, spe_evextsh)
BU_SPE_1 (EVFSABS, "evfsabs", CONST, spe_evfsabs)
BU_SPE_1 (EVFSCFSF, "evfscfsf", CONST, spe_evfscfsf)
BU_SPE_1 (EVFSCFSI, "evfscfsi", CONST, spe_evfscfsi)
BU_SPE_1 (EVFSCFUF, "evfscfuf", CONST, spe_evfscfuf)
BU_SPE_1 (EVFSCFUI, "evfscfui", CONST, spe_evfscfui)
BU_SPE_1 (EVFSCTSF, "evfsctsf", CONST, spe_evfsctsf)
BU_SPE_1 (EVFSCTSI, "evfsctsi", CONST, spe_evfsctsi)
BU_SPE_1 (EVFSCTSIZ, "evfsctsiz", CONST, spe_evfsctsiz)
BU_SPE_1 (EVFSCTUF, "evfsctuf", CONST, spe_evfsctuf)
BU_SPE_1 (EVFSCTUI, "evfsctui", CONST, spe_evfsctui)
BU_SPE_1 (EVFSCTUIZ, "evfsctuiz", CONST, spe_evfsctuiz)
BU_SPE_1 (EVFSNABS, "evfsnabs", CONST, spe_evfsnabs)
BU_SPE_1 (EVFSNEG, "evfsneg", CONST, spe_evfsneg)
BU_SPE_1 (EVMRA, "evmra", CONST, spe_evmra)
BU_SPE_1 (EVNEG, "evneg", CONST, negv2si2)
BU_SPE_1 (EVRNDW, "evrndw", CONST, spe_evrndw)
BU_SPE_1 (EVSUBFSMIAAW, "evsubfsmiaaw", CONST, spe_evsubfsmiaaw)
BU_SPE_1 (EVSUBFSSIAAW, "evsubfssiaaw", CONST, spe_evsubfssiaaw)
BU_SPE_1 (EVSUBFUMIAAW, "evsubfumiaaw", CONST, spe_evsubfumiaaw)
BU_SPE_1 (EVSUBFUSIAAW, "evsubfusiaaw", CONST, spe_evsubfusiaaw)
/* SPE builtins that are handled as special cases. */
BU_SPE_X (EVLDD, "evldd", MISC)
BU_SPE_X (EVLDDX, "evlddx", MISC)
BU_SPE_X (EVLDH, "evldh", MISC)
BU_SPE_X (EVLDHX, "evldhx", MISC)
BU_SPE_X (EVLDW, "evldw", MISC)
BU_SPE_X (EVLDWX, "evldwx", MISC)
BU_SPE_X (EVLHHESPLAT, "evlhhesplat", MISC)
BU_SPE_X (EVLHHESPLATX, "evlhhesplatx", MISC)
BU_SPE_X (EVLHHOSSPLAT, "evlhhossplat", MISC)
BU_SPE_X (EVLHHOSSPLATX, "evlhhossplatx", MISC)
BU_SPE_X (EVLHHOUSPLAT, "evlhhousplat", MISC)
BU_SPE_X (EVLHHOUSPLATX, "evlhhousplatx", MISC)
BU_SPE_X (EVLWHE, "evlwhe", MISC)
BU_SPE_X (EVLWHEX, "evlwhex", MISC)
BU_SPE_X (EVLWHOS, "evlwhos", MISC)
BU_SPE_X (EVLWHOSX, "evlwhosx", MISC)
BU_SPE_X (EVLWHOU, "evlwhou", MISC)
BU_SPE_X (EVLWHOUX, "evlwhoux", MISC)
BU_SPE_X (EVLWHSPLAT, "evlwhsplat", MISC)
BU_SPE_X (EVLWHSPLATX, "evlwhsplatx", MISC)
BU_SPE_X (EVLWWSPLAT, "evlwwsplat", MISC)
BU_SPE_X (EVLWWSPLATX, "evlwwsplatx", MISC)
BU_SPE_X (EVSPLATFI, "evsplatfi", MISC)
BU_SPE_X (EVSPLATI, "evsplati", MISC)
BU_SPE_X (EVSTDD, "evstdd", MISC)
BU_SPE_X (EVSTDDX, "evstddx", MISC)
BU_SPE_X (EVSTDH, "evstdh", MISC)
BU_SPE_X (EVSTDHX, "evstdhx", MISC)
BU_SPE_X (EVSTDW, "evstdw", MISC)
BU_SPE_X (EVSTDWX, "evstdwx", MISC)
BU_SPE_X (EVSTWHE, "evstwhe", MISC)
BU_SPE_X (EVSTWHEX, "evstwhex", MISC)
BU_SPE_X (EVSTWHO, "evstwho", MISC)
BU_SPE_X (EVSTWHOX, "evstwhox", MISC)
BU_SPE_X (EVSTWWE, "evstwwe", MISC)
BU_SPE_X (EVSTWWEX, "evstwwex", MISC)
BU_SPE_X (EVSTWWO, "evstwwo", MISC)
BU_SPE_X (EVSTWWOX, "evstwwox", MISC)
BU_SPE_X (MFSPEFSCR, "mfspefscr", MISC)
BU_SPE_X (MTSPEFSCR, "mtspefscr", MISC)
/* Power7 builtins, that aren't VSX instructions. */
BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD,

4
gcc/config/rs6000/rs6000-c.c
View File

@ -611,10 +611,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
/* options from the builtin masks. */
/* Note that RS6000_BTM_SPE is enabled only if TARGET_SPE
(e.g. -mspe). */
if ((bu_mask & RS6000_BTM_SPE) != 0)
rs6000_define_or_undefine_macro (define_p, "__SPE__");
/* Note that RS6000_BTM_PAIRED is enabled only if
TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired). */
if ((bu_mask & RS6000_BTM_PAIRED) != 0)

1
gcc/config/rs6000/rs6000-protos.h
View File

@ -41,7 +41,6 @@ extern int small_data_operand (rtx, machine_mode);
extern bool mem_operand_gpr (rtx, machine_mode);
extern bool mem_operand_ds_form (rtx, machine_mode);
extern bool toc_relative_expr_p (const_rtx, bool);
extern bool invalid_e500_subreg (rtx, machine_mode);
extern void validate_condition_mode (enum rtx_code, machine_mode);
extern bool legitimate_constant_pool_address_p (const_rtx, machine_mode,
bool);

1417
gcc/config/rs6000/rs6000.c
View File

File diff suppressed because it is too large Load Diff

44
gcc/config/rs6000/rs6000.h
View File

@ -569,8 +569,6 @@ extern int rs6000_vector_align[];
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
@ -704,7 +702,7 @@ extern int rs6000_vector_align[];
the compiler for those builtins, and those machines don't support altivec or
VSX. */
#define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
#define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \
&& ((TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \
@ -869,7 +867,6 @@ extern unsigned char rs6000_recip_bits[];
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_VSX_WORD 16
#define UNITS_PER_SPE_WORD 8
#define UNITS_PER_PAIRED_WORD 8
/* Type used for ptrdiff_t, as a string used in a declaration. */
@ -971,8 +968,7 @@ enum data_align { align_abi, align_opt, align_both };
#define DATA_ALIGNMENT(TYPE, ALIGN) \
rs6000_data_alignment (TYPE, ALIGN, align_opt)
/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
64 bits. */
/* Align vectors to 128 bits. */
#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
rs6000_data_alignment (TYPE, ALIGN, align_abi)
@ -983,9 +979,8 @@ enum data_align { align_abi, align_opt, align_both };
/* Define this macro to be the value 1 if unaligned accesses have a cost
many times greater than aligned accesses, for example if they are
emulated in a trap handler. */
/* Altivec vector memory instructions simply ignore the low bits; SPE vector
memory instructions trap on unaligned accesses; VSX memory instructions are
aligned to 4 or 8 bytes. */
/* Altivec vector memory instructions simply ignore the low bits; VSX memory
instructions are aligned to 4 or 8 bytes. */
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
(STRICT_ALIGNMENT \
|| (!TARGET_EFFICIENT_UNALIGNED_VSX \
@ -1027,12 +1022,7 @@ enum data_align { align_abi, align_opt, align_both };
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
/* True if register is an SPE High register. */
#define SPE_HIGH_REGNO_P(N) \
((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
/* SPE high registers added as hard regs.
The sfp register and 3 HTM registers
/* The sfp register and 3 HTM registers
aren't included in DWARF_FRAME_REGISTERS. */
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
@ -1227,9 +1217,6 @@ enum data_align { align_abi, align_opt, align_both };
#define INT_REGNO_P(N) \
((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
/* SPE SIMD registers are just the GPRs. */
#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
/* PAIRED SIMD registers are just the FPRs. */
#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
@ -1305,12 +1292,6 @@ enum data_align { align_abi, align_opt, align_both };
(ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
|| (MODE) == V2DImode || (MODE) == V1TImode)
#define SPE_VECTOR_MODE(MODE) \
((MODE) == V4HImode \
|| (MODE) == V2SFmode \
|| (MODE) == V1DImode \
|| (MODE) == V2SImode)
#define PAIRED_VECTOR_MODE(MODE) \
((MODE) == V2SFmode)
@ -1347,9 +1328,9 @@ enum data_align { align_abi, align_opt, align_both };
? GET_MODE_CLASS (MODE2) == MODE_CC \
: GET_MODE_CLASS (MODE2) == MODE_CC \
? 0 \
: SPE_VECTOR_MODE (MODE1) \
? SPE_VECTOR_MODE (MODE2) \
: SPE_VECTOR_MODE (MODE2) \
: PAIRED_VECTOR_MODE (MODE1) \
? PAIRED_VECTOR_MODE (MODE2) \
: PAIRED_VECTOR_MODE (MODE2) \
? 0 \
: 1)
@ -2684,7 +2665,7 @@ extern int frame_pointer_needed;
#define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
/* Builtin targets. For now, we reuse the masks for those options that are in
target flags, and pick three random bits for SPE, paired and ldbl128 which
target flags, and pick two random bits for paired and ldbl128, which
aren't in target_flags. */
#define RS6000_BTM_ALWAYS 0 /* Always enabled. */
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
@ -2695,7 +2676,6 @@ extern int frame_pointer_needed;
#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_SPE MASK_STRING /* E500 */
#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
@ -2736,11 +2716,9 @@ extern int frame_pointer_needed;
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
@ -2749,11 +2727,9 @@ extern int frame_pointer_needed;
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
enum rs6000_builtins
@ -2769,11 +2745,9 @@ enum rs6000_builtins
#undef RS6000_BUILTIN_3
#undef RS6000_BUILTIN_A
#undef RS6000_BUILTIN_D
#undef RS6000_BUILTIN_E
#undef RS6000_BUILTIN_H
#undef RS6000_BUILTIN_P
#undef RS6000_BUILTIN_Q
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
enum rs6000_builtin_type_index

2
gcc/config/rs6000/rs6000.md
View File

@ -56,8 +56,6 @@
(TFHAR_REGNO 114)
(TFIAR_REGNO 115)
(TEXASR_REGNO 116)
(FIRST_SPE_HIGH_REGNO 117)
(LAST_SPE_HIGH_REGNO 148)
])
;;

8
gcc/config/rs6000/rs6000.opt
View File

@ -381,14 +381,6 @@ mabi=no-altivec
Target RejectNegative Var(rs6000_altivec_abi, 0)
Do not use the AltiVec ABI extensions.
mabi=spe
Target RejectNegative Var(rs6000_spe_abi) Save
Use the SPE ABI extensions.
mabi=no-spe
Target RejectNegative Var(rs6000_spe_abi, 0)
Do not use the SPE ABI extensions.
mabi=elfv1
Target RejectNegative Var(rs6000_elf_abi, 1) Save
Use the ELFv1 ABI.

2767
gcc/config/rs6000/spe.md
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File diff suppressed because it is too large Load Diff

95
gcc/config/rs6000/vector.md
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@ -1309,98 +1309,3 @@
emit_insn (gen_vsx_extract_<VEC_F:mode> (operand0, vec, elt));
DONE;
})
;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
(define_expand "absv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
"TARGET_PAIRED_FLOAT || TARGET_SPE"
"")
(define_expand "negv2sf2"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
(neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
"TARGET_PAIRED_FLOAT || TARGET_SPE"
"")
(define_expand "addv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
(plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
"TARGET_PAIRED_FLOAT || TARGET_SPE"
"
{
if (TARGET_SPE)
{
/* We need to make a note that we clobber SPEFSCR. */
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
emit_insn (par);
DONE;
}
}")
(define_expand "subv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
(minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
"TARGET_PAIRED_FLOAT || TARGET_SPE"
"
{
if (TARGET_SPE)
{
/* We need to make a note that we clobber SPEFSCR. */
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
emit_insn (par);
DONE;
}
}")
(define_expand "mulv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
(mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
"TARGET_PAIRED_FLOAT || TARGET_SPE"
"
{
if (TARGET_SPE)
{
/* We need to make a note that we clobber SPEFSCR. */
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
emit_insn (par);
DONE;
}
}")
(define_expand "divv2sf3"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "")
(div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
(match_operand:V2SF 2 "gpc_reg_operand" "")))]
"TARGET_PAIRED_FLOAT || TARGET_SPE"
"
{
if (TARGET_SPE)
{
/* We need to make a note that we clobber SPEFSCR. */
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
XVECEXP (par, 0, 0) = gen_rtx_SET (operands[0],
gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
emit_insn (par);
DONE;
}
}")