mirror of git://gcc.gnu.org/git/gcc.git
rs6000-protos.h (rs6000_split_vec_extract_var): New declaration.
[gcc] 2016-07-28 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000-protos.h (rs6000_split_vec_extract_var): New declaration. * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add support for vec_extract of vector double or vector long having a variable element number on 64-bit ISA 2.07 systems or newer. * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Likewise. (rs6000_split_vec_extract_var): New function to split a vec_extract built-in function with variable element number. (rtx_is_swappable_p): Variable vec_extracts and shifts are not swappable. * config/rs6000/vsx.md (UNSPEC_VSX_VSLO): New unspec. (UNSPEC_VSX_EXTRACT): Likewise. (vsx_extract_<mode>, VSX_D iterator): Fix constraints to allow direct move instructions to be generated on 64-bit ISA 2.07 systems and newer, and to take advantage of the ISA 3.0 MFVSRLD instruction. (vsx_vslo_<mode>): New insn to do VSLO on V2DFmode and V2DImode arguments for vec_extract variable element. (vsx_extract_<mode>_var, VSX_D iterator): New insn to support vec_extract with variable element on V2DFmode and V2DImode vectors. * config/rs6000/rs6000.h (TARGET_VEXTRACTUB): Remove -mupper-regs-df requirement, since it isn't needed. (TARGET_DIRECT_MOVE_64BIT): New macro to say whether we can do direct moves on 64-bit systems, which allows optimization of vec_extract on 64-bit ISA 2.07 systems and newer. [gcc/testsuite] 2016-07-28 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/vec-extract-1.c: New test. From-SVN: r238838
This commit is contained in:
Michael Meissner
Michael Meissner
parent
1a2196e484
commit
e0d321856b
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@ -1,3 +1,33 @@
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2016-07-28 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/rs6000-protos.h (rs6000_split_vec_extract_var):
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New declaration.
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* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
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Add support for vec_extract of vector double or vector long having
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a variable element number on 64-bit ISA 2.07 systems or newer.
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* config/rs6000/rs6000.c (rs6000_expand_vector_extract):
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Likewise.
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(rs6000_split_vec_extract_var): New function to split a
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vec_extract built-in function with variable element number.
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(rtx_is_swappable_p): Variable vec_extracts and shifts are not
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swappable.
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* config/rs6000/vsx.md (UNSPEC_VSX_VSLO): New unspec.
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(UNSPEC_VSX_EXTRACT): Likewise.
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(vsx_extract_<mode>, VSX_D iterator): Fix constraints to allow
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direct move instructions to be generated on 64-bit ISA 2.07
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systems and newer, and to take advantage of the ISA 3.0 MFVSRLD
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instruction.
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(vsx_vslo_<mode>): New insn to do VSLO on V2DFmode and V2DImode
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arguments for vec_extract variable element.
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(vsx_extract_<mode>_var, VSX_D iterator): New insn to support
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vec_extract with variable element on V2DFmode and V2DImode
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vectors.
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* config/rs6000/rs6000.h (TARGET_VEXTRACTUB): Remove
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-mupper-regs-df requirement, since it isn't needed.
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(TARGET_DIRECT_MOVE_64BIT): New macro to say whether we can
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do direct moves on 64-bit systems, which allows optimization of
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vec_extract on 64-bit ISA 2.07 systems and newer.
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2016-07-28 Kristina Martsenko <kristina.martsenko@arm.com>
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2016-07-28 Wilco Dijkstra <wdijkstr@arm.com>
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@ -5105,29 +5105,61 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
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arg2);
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}
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/* If we can use the VSX xxpermdi instruction, use that for extract. */
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/* See if we can optimize vec_extracts with the current VSX instruction
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set. */
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mode = TYPE_MODE (arg1_type);
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if ((mode == V2DFmode || mode == V2DImode) && VECTOR_MEM_VSX_P (mode)
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&& TREE_CODE (arg2) == INTEGER_CST
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&& wi::ltu_p (arg2, 2))
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if (VECTOR_MEM_VSX_P (mode))
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{
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tree call = NULL_TREE;
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int nunits = GET_MODE_NUNITS (mode);
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if (mode == V2DFmode)
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
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else if (mode == V2DImode)
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
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/* If the second argument is an integer constant, if the value is in
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the expected range, generate the built-in code if we can. We need
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64-bit and direct move to extract the small integer vectors. */
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if (TREE_CODE (arg2) == INTEGER_CST && wi::ltu_p (arg2, nunits))
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{
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switch (mode)
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{
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default:
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break;
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case V1TImode:
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
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break;
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case V2DFmode:
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
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break;
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case V2DImode:
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
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break;
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}
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}
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/* If the second argument is variable, we can optimize it if we are
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generating 64-bit code on a machine with direct move. */
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else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
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{
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switch (mode)
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{
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default:
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break;
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case V2DFmode:
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
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break;
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case V2DImode:
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call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
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break;
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}
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}
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if (call)
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return build_call_expr (call, 2, arg1, arg2);
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}
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else if (mode == V1TImode && VECTOR_MEM_VSX_P (mode)
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&& TREE_CODE (arg2) == INTEGER_CST
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&& wi::eq_p (arg2, 0))
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{
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tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
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return build_call_expr (call, 2, arg1, arg2);
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}
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/* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
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arg1_inner_type = TREE_TYPE (arg1_type);
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@ -62,6 +62,7 @@ extern void rs6000_expand_vector_init (rtx, rtx);
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extern void paired_expand_vector_init (rtx, rtx);
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extern void rs6000_expand_vector_set (rtx, rtx, int);
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extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
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extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
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extern bool altivec_expand_vec_perm_const (rtx op[4]);
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extern void altivec_expand_vec_perm_le (rtx op[4]);
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extern bool rs6000_expand_vec_perm_const (rtx op[4]);
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@ -6959,8 +6959,31 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
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emit_insn (gen_vsx_extract_v4si (target, vec, elt));
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return;
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}
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else
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break;
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break;
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}
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}
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else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
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&& TARGET_DIRECT_MOVE_64BIT)
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{
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if (GET_MODE (elt) != DImode)
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{
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rtx tmp = gen_reg_rtx (DImode);
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convert_move (tmp, elt, 0);
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elt = tmp;
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}
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switch (mode)
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{
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case V2DFmode:
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emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
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return;
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case V2DImode:
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emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
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return;
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default:
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gcc_unreachable ();
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}
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}
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@ -6978,6 +7001,99 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
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emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
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}
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/* Split a variable vec_extract operation into the component instructions. */
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void
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rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
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rtx tmp_altivec)
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{
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machine_mode mode = GET_MODE (src);
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machine_mode scalar_mode = GET_MODE (dest);
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unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
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int byte_shift = exact_log2 (scalar_size);
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gcc_assert (byte_shift >= 0);
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if (REG_P (src) || SUBREG_P (src))
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{
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int bit_shift = byte_shift + 3;
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rtx element2;
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gcc_assert (REG_P (tmp_gpr) && REG_P (tmp_altivec));
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/* For little endian, adjust element ordering. For V2DI/V2DF, we can use
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an XOR, otherwise we need to subtract. The shift amount is so VSLO
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will shift the element into the upper position (adding 3 to convert a
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byte shift into a bit shift). */
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if (scalar_size == 8)
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{
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if (!VECTOR_ELT_ORDER_BIG)
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{
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emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
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element2 = tmp_gpr;
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}
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else
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element2 = element;
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/* Generate RLDIC directly to shift left 6 bits and retrieve 1
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bit. */
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emit_insn (gen_rtx_SET (tmp_gpr,
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gen_rtx_AND (DImode,
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gen_rtx_ASHIFT (DImode,
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element2,
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GEN_INT (6)),
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GEN_INT (64))));
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}
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else
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{
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if (!VECTOR_ELT_ORDER_BIG)
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{
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rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
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emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
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emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
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element2 = tmp_gpr;
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}
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else
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element2 = element;
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emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
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}
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/* Get the value into the lower byte of the Altivec register where VSLO
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expects it. */
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if (TARGET_P9_VECTOR)
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emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
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else if (can_create_pseudo_p ())
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emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
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else
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{
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rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
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emit_move_insn (tmp_di, tmp_gpr);
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emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
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}
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/* Do the VSLO to get the value into the final location. */
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switch (mode)
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{
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case V2DFmode:
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emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
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return;
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case V2DImode:
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emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
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return;
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default:
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gcc_unreachable ();
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}
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return;
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}
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else
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gcc_unreachable ();
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}
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/* Return TRUE if OP is an invalid SUBREG operation on the e500. */
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bool
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@ -38640,6 +38756,7 @@ rtx_is_swappable_p (rtx op, unsigned int *special)
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case UNSPEC_VSX_CVDPSPN:
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case UNSPEC_VSX_CVSPDP:
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case UNSPEC_VSX_CVSPDPN:
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case UNSPEC_VSX_EXTRACT:
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return 0;
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case UNSPEC_VSPLT_DIRECT:
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*special = SH_SPLAT;
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@ -602,7 +602,6 @@ extern int rs6000_vector_align[];
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#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
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&& TARGET_POWERPC64)
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#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
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&& TARGET_UPPER_REGS_DF \
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&& TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
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/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
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@ -761,6 +760,14 @@ extern int rs6000_vector_align[];
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&& TARGET_SINGLE_FLOAT \
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&& TARGET_DOUBLE_FLOAT)
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/* Macro to say whether we can do optimization where we need to do parts of the
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calculation in 64-bit GPRs and then is transfered to the vector
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registers. */
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#define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
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&& TARGET_P8_VECTOR \
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&& TARGET_POWERPC64 \
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&& TARGET_UPPER_REGS_DI)
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/* Whether the various reciprocal divide/square root estimate instructions
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exist, and whether we should automatically generate code for the instruction
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by default. */
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@ -309,6 +309,8 @@
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UNSPEC_VSX_XVCVDPUXDS
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UNSPEC_VSX_SIGN_EXTEND
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UNSPEC_P9_MEMORY
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UNSPEC_VSX_VSLO
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UNSPEC_VSX_EXTRACT
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])
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;; VSX moves
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@ -2118,16 +2120,13 @@
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;; register was picked. Limit the scalar value to FPRs for now.
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(define_insn "vsx_extract_<mode>"
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[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand"
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"=d, wm, wo, d")
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[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d, wr, wr")
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(vec_select:<VS_scalar>
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(match_operand:VSX_D 1 "gpc_reg_operand"
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"<VSa>, <VSa>, <VSa>, <VSa>")
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(match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>, <VSa>, wm, wo")
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(parallel
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[(match_operand:QI 2 "const_0_to_1_operand"
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"wD, wD, wL, n")])))]
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[(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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int element = INTVAL (operands[2]);
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@ -2205,6 +2204,34 @@
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[(set_attr "type" "fpstore")
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(set_attr "length" "4")])
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;; Variable V2DI/V2DF extract shift
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(define_insn "vsx_vslo_<mode>"
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[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v")
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(unspec:<VS_scalar> [(match_operand:VSX_D 1 "gpc_reg_operand" "v")
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(match_operand:V2DI 2 "gpc_reg_operand" "v")]
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UNSPEC_VSX_VSLO))]
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"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
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"vslo %0,%1,%2"
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[(set_attr "type" "vecperm")])
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;; Variable V2DI/V2DF extract
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(define_insn_and_split "vsx_extract_<mode>_var"
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[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v")
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(unspec:<VS_scalar> [(match_operand:VSX_D 1 "input_operand" "v")
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(match_operand:DI 2 "gpc_reg_operand" "r")]
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UNSPEC_VSX_EXTRACT))
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(clobber (match_scratch:DI 3 "=r"))
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(clobber (match_scratch:V2DI 4 "=&v"))]
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"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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rs6000_split_vec_extract_var (operands[0], operands[1], operands[2],
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operands[3], operands[4]);
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DONE;
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})
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;; Extract a SF element from V4SF
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(define_insn_and_split "vsx_extract_v4sf"
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[(set (match_operand:SF 0 "vsx_register_operand" "=f,f")
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|
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@ -1,3 +1,7 @@
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2016-07-28 Michael Meissner <meissner@linux.vnet.ibm.com>
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* gcc.target/powerpc/vec-extract-1.c: New test.
|
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2016-07-28 Steven G. Kargl <kargl@gcc.gnu.org>
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PR fortran/71799
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|
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@ -0,0 +1,27 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
|
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */
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#include <altivec.h>
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double
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add_double (vector double a, int n)
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{
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return vec_extract (a, n) + 1.0;
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}
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long
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add_long (vector long a, int n)
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{
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return vec_extract (a, n) + 1;
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}
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/* { dg-final { scan-assembler "vslo" } } */
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/* { dg-final { scan-assembler "mtvsrd" } } */
|
||||
/* { dg-final { scan-assembler "mfvsrd" } } */
|
||||
/* { dg-final { scan-assembler-not "stxvd2x" } } */
|
||||
/* { dg-final { scan-assembler-not "stxvx" } } */
|
||||
/* { dg-final { scan-assembler-not "stxv" } } */
|
||||
/* { dg-final { scan-assembler-not "ldx" } } */
|
||||
Loading…
Reference in New Issue