mirror of git://gcc.gnu.org/git/gcc.git
invoke.texi ([-fplan9-extensions]): Add/fix @opindex.
2015-01-03 Sandra Loosemore <sandra@codesourcery.com> gcc/ * doc/invoke.texi ([-fplan9-extensions]): Add/fix @opindex. ([-fvtv-debug]): Likewise. ([-Wc++-compat]): Likewise. ([-Wc++11-compat]): Likewise. ([-Wc++14-compat]): Likewise. ([-Wno-sized-deallocation]): Likewise. ([-femit-class-debug-always]): Likewise. ([-femit-struct-debug-detailed]): Likewise. ([-fno-keep-inline-dllexport]): Likewise. ([-fira-algorithm]): Likewise. ([-fira-region]): Likewise. ([-flra-remat]): Likewise. ([-fipa-ra]): Likewise. ([-fhoist-adjacent-loads]): Likewise. ([-fisolate-erroneous-paths-dereference]): Likewise. ([-fisolate-erroneous-paths-attribute]): Likewise. ([-ftree-switch-conversion]): Likewise. ([-ftree-tail-merge]): Likewise. ([-ftree-loop-if-convert]): Likewise. ([-ftree-loop-if-convert-stores]): Likewise. ([-ftree-loop-distribution]): Likewise. ([-ftree-loop-distribute-patterns]): Likewise. ([-flto-compression-level]): Likewise. ([-flto-report]): Likewise. ([-flto-report-wpa]): Likewise. ([-fuse-linker-plugin]): Likewise. ([-mfix-cortex-a53-835769]): Likewise. ([-mno-fix-cortex-a53-835769]): Likewise. ([-mmmx]...[-mno-3dnow]): Remove the -mno- forms from the explicit listing; add a note to the discussion indicating they exist. Reorder table to group similar options. Add missing @opindex entries. Add @need commands throughout the table to allow it to be split across multiple pages. ([-m8bit-idiv]): Fix @opindex. ([-mavx256-split-unaligned-load]): Likewise. ([-mavx256-split-unaligned-store]): Likewise. ([-mstack-protector-guard]): Likewise. ([-mcpu=]): Likewise. ([-mcpu]): Likewise. ([-mpointer-size=]): Likewise. From-SVN: r219164
This commit is contained in:
Sandra Loosemore
Sandra Loosemore
parent
846ef40a53
commit
e1a77fb6ec
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@ -1,3 +1,46 @@
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2015-01-03 Sandra Loosemore <sandra@codesourcery.com>
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* doc/invoke.texi ([-fplan9-extensions]): Add/fix @opindex.
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([-fvtv-debug]): Likewise.
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([-Wc++-compat]): Likewise.
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([-Wc++11-compat]): Likewise.
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([-Wc++14-compat]): Likewise.
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([-Wno-sized-deallocation]): Likewise.
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([-femit-class-debug-always]): Likewise.
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([-femit-struct-debug-detailed]): Likewise.
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([-fno-keep-inline-dllexport]): Likewise.
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([-fira-algorithm]): Likewise.
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([-fira-region]): Likewise.
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([-flra-remat]): Likewise.
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([-fipa-ra]): Likewise.
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([-fhoist-adjacent-loads]): Likewise.
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([-fisolate-erroneous-paths-dereference]): Likewise.
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([-fisolate-erroneous-paths-attribute]): Likewise.
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([-ftree-switch-conversion]): Likewise.
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([-ftree-tail-merge]): Likewise.
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([-ftree-loop-if-convert]): Likewise.
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([-ftree-loop-if-convert-stores]): Likewise.
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([-ftree-loop-distribution]): Likewise.
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([-ftree-loop-distribute-patterns]): Likewise.
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([-flto-compression-level]): Likewise.
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([-flto-report]): Likewise.
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([-flto-report-wpa]): Likewise.
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([-fuse-linker-plugin]): Likewise.
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([-mfix-cortex-a53-835769]): Likewise.
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([-mno-fix-cortex-a53-835769]): Likewise.
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([-mmmx]...[-mno-3dnow]): Remove the -mno- forms from the
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explicit listing; add a note to the discussion indicating they
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exist. Reorder table to group similar options. Add missing
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@opindex entries. Add @need commands throughout the table to
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allow it to be split across multiple pages.
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([-m8bit-idiv]): Fix @opindex.
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([-mavx256-split-unaligned-load]): Likewise.
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([-mavx256-split-unaligned-store]): Likewise.
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([-mstack-protector-guard]): Likewise.
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([-mcpu=]): Likewise.
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([-mcpu]): Likewise.
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([-mpointer-size=]): Likewise.
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2015-01-03 John David Anglin <danglin@gcc.gnu.org>
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* config/pa/pa.md (decrement_and_branch_until_zero): Use `Q' constraint
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@ -1942,7 +1942,9 @@ fields within structs/unions}, for details.
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Note that this option is off for all targets but i?86 and x86_64
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targets using ms-abi.
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@item -fplan9-extensions
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@opindex fplan9-extensions
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Accept some non-standard constructs used in Plan 9 code.
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This enables @option{-fms-extensions}, permits passing pointers to
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@ -2453,7 +2455,7 @@ values specified, 'none' will take highest priority over both 'std' and
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'preinit'; 'preinit' will take priority over 'std'.
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@item -fvtv-debug
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@opindex (fvtv-debug)
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@opindex fvtv-debug
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Causes debug versions of the runtime functions for the vtable verification
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feature to be called. This assumes the @option{-fvtable-verify=std} or
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@option{-fvtable-verify=preinit} has been used. This flag will also cause the
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@ -4622,17 +4624,20 @@ and so on. This option is independent of the standards mode. Warnings are
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disabled in the expression that follows @code{__extension__}.
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@item -Wc++-compat @r{(C and Objective-C only)}
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@opindex Wc++-compat
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Warn about ISO C constructs that are outside of the common subset of
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ISO C and ISO C++, e.g.@: request for implicit conversion from
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@code{void *} to a pointer to non-@code{void} type.
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@item -Wc++11-compat @r{(C++ and Objective-C++ only)}
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@opindex Wc++11-compat
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Warn about C++ constructs whose meaning differs between ISO C++ 1998
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and ISO C++ 2011, e.g., identifiers in ISO C++ 1998 that are keywords
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in ISO C++ 2011. This warning turns on @option{-Wnarrowing} and is
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enabled by @option{-Wall}.
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@item -Wc++14-compat @r{(C++ and Objective-C++ only)}
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@opindex Wc++14-compat
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Warn about C++ constructs whose meaning differs between ISO C++ 2011
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and ISO C++ 2014. This warning is enabled by @option{-Wall}.
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@ -4797,7 +4802,7 @@ real to lower precision real values. This option is also enabled by
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@item -Wsized-deallocation @r{(C++ and Objective-C++ only)}
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@opindex Wsized-deallocation
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@opindex -Wno-sized-deallocation
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@opindex Wno-sized-deallocation
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Warn about a definition of an unsized deallocation function
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@smallexample
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void operator delete (void *) noexcept;
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@ -5411,6 +5416,7 @@ Produce debugging information in stabs format (if that is supported),
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for only symbols that are actually used.
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@item -femit-class-debug-always
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@opindex femit-class-debug-always
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Instead of emitting debugging information for a C++ class in only one
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object file, emit it in all object files using the class. This option
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should be used only with debuggers that are unable to handle the way GCC
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@ -5827,6 +5833,7 @@ See @option{-femit-struct-debug-detailed} for more detailed control.
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This option works only with DWARF 2.
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@item -femit-struct-debug-detailed@r{[}=@var{spec-list}@r{]}
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@opindex femit-struct-debug-detailed
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Specify the struct-like types
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for which the compiler generates debug information.
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The intent is to reduce duplicate struct debug information
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@ -7489,7 +7496,7 @@ of assembly instructions and as such its exact meaning might change from one
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release to an another.
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@item -fno-keep-inline-dllexport
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@opindex -fno-keep-inline-dllexport
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@opindex fno-keep-inline-dllexport
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This is a more fine-grained version of @option{-fkeep-inline-functions},
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which applies only to functions that are declared using the @code{dllexport}
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attribute or declspec (@xref{Function Attributes,,Declaring Attributes of
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@ -7815,6 +7822,7 @@ shrinkage. This is helpful for fast processors with small or moderate
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size register sets.
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@item -fira-algorithm=@var{algorithm}
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@opindex fira-algorithm
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Use the specified coloring algorithm for the integrated register
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allocator. The @var{algorithm} argument can be @samp{priority}, which
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specifies Chow's priority coloring, or @samp{CB}, which specifies
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@ -7823,6 +7831,7 @@ for all architectures, but for those targets that do support it, it is
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the default because it generates better code.
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@item -fira-region=@var{region}
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@opindex fira-region
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Use specified regions for the integrated register allocator. The
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@var{region} argument should be one of the following:
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@ -7884,7 +7893,7 @@ The default value is 5. If the value @var{n} is greater or equal to 10,
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the dump output is sent to stderr using the same format as @var{n} minus 10.
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@item -flra-remat
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@opindex fcaller-saves
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@opindex flra-remat
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Enable CFG-sensitive rematerialization in LRA. Instead of loading
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values of spilled pseudos, LRA tries to rematerialize (recalculate)
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values if it is profitable.
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@ -8101,6 +8110,7 @@ and then tries to find ways to combine them.
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Enabled by default at @option{-O1} and higher.
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@item -fipa-ra
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@opindex fipa-ra
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Use caller save registers for allocation if those registers are not used by
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any called function. In that case it is not necessary to save and restore
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them around calls. This is only possible if called functions are part of
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@ -8149,7 +8159,7 @@ Perform hoisting of loads from conditional pointers on trees. This
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pass is enabled by default at @option{-O} and higher.
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@item -fhoist-adjacent-loads
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@opindex hoist-adjacent-loads
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@opindex fhoist-adjacent-loads
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Speculatively hoist loads from both branches of an if-then-else if the
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loads are from adjacent locations in the same structure and the target
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architecture has a conditional move instruction. This flag is enabled
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@ -8221,11 +8231,13 @@ equivalences that are found only by GCC and equivalences found only by Gold.
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This flag is enabled by default at @option{-O2} and @option{-Os}.
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@item -fisolate-erroneous-paths-dereference
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@opindex fisolate-erroneous-paths-dereference
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Detect paths which trigger erroneous or undefined behaviour due to
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dereferencing a NULL pointer. Isolate those paths from the main control
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flow and turn the statement with erroneous or undefined behaviour into a trap.
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@item -fisolate-erroneous-paths-attribute
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@opindex fisolate-erroneous-paths-attribute
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Detect paths which trigger erroneous or undefined behaviour due a NULL value
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being used in a way which is forbidden by a @code{returns_nonnull} or @code{nonnull}
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attribute. Isolate those paths from the main control flow and turn the
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@ -8256,11 +8268,13 @@ Perform pattern matching on SSA PHI nodes to optimize conditional
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code. This pass is enabled by default at @option{-O} and higher.
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@item -ftree-switch-conversion
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@opindex ftree-switch-conversion
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Perform conversion of simple initializations in a switch to
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initializations from a scalar array. This flag is enabled by default
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at @option{-O2} and higher.
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@item -ftree-tail-merge
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@opindex ftree-tail-merge
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Look for identical code sequences. When found, replace one with a jump to the
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other. This optimization is known as tail merging or cross jumping. This flag
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is enabled by default at @option{-O2} and higher. The compilation time
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@ -8438,6 +8452,7 @@ Compare the results of several data dependence analyzers. This option
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is used for debugging the data dependence analyzers.
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@item -ftree-loop-if-convert
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@opindex ftree-loop-if-convert
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Attempt to transform conditional jumps in the innermost loops to
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branch-less equivalents. The intent is to remove control-flow from
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the innermost loops in order to improve the ability of the
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@ -8445,6 +8460,7 @@ vectorization pass to handle these loops. This is enabled by default
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if vectorization is enabled.
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@item -ftree-loop-if-convert-stores
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@opindex ftree-loop-if-convert-stores
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Attempt to also if-convert conditional jumps containing memory writes.
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This transformation can be unsafe for multi-threaded programs as it
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transforms conditional memory writes into unconditional memory writes.
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@ -8462,6 +8478,7 @@ for (i = 0; i < N; i++)
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potentially producing data races.
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@item -ftree-loop-distribution
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@opindex ftree-loop-distribution
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Perform loop distribution. This flag can improve cache performance on
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big loop bodies and allow further loop optimizations, like
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parallelization or vectorization, to take place. For example, the loop
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@ -8482,6 +8499,7 @@ ENDDO
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@end smallexample
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@item -ftree-loop-distribute-patterns
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@opindex ftree-loop-distribute-patterns
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Perform loop distribution of patterns that can be code generated with
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calls to a library. This flag is enabled by default at @option{-O3}.
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@ -9189,6 +9207,7 @@ at linktime. This increases size of LTO object files, but enable
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diagnostics about One Definition Rule violations.
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@item -flto-compression-level=@var{n}
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@opindex flto-compression-level
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This option specifies the level of compression used for intermediate
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language written to LTO object files, and is only meaningful in
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conjunction with LTO mode (@option{-flto}). Valid
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@ -9197,6 +9216,7 @@ outside this range are clamped to either 0 or 9. If the option is not
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given, a default balanced compression setting is used.
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@item -flto-report
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@opindex flto-report
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Prints a report with internal details on the workings of the link-time
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optimizer. The contents of this report vary from version to version.
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It is meant to be useful to GCC developers when processing object
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@ -9205,10 +9225,12 @@ files in LTO mode (via @option{-flto}).
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Disabled by default.
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@item -flto-report-wpa
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@opindex flto-report-wpa
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Like @option{-flto-report}, but only print for the WPA phase of Link
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Time Optimization.
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@item -fuse-linker-plugin
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@opindex fuse-linker-plugin
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Enables the use of a linker plugin during link-time optimization. This
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option relies on plugin support in the linker, which is available in gold
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or in GNU ld 2.21 or newer.
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@ -11983,8 +12005,8 @@ of TLS variables.
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@item -mfix-cortex-a53-835769
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@itemx -mno-fix-cortex-a53-835769
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@opindex -mfix-cortex-a53-835769
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@opindex -mno-fix-cortex-a53-835769
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@opindex mfix-cortex-a53-835769
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@opindex mno-fix-cortex-a53-835769
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Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
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This will involve inserting a NOP instruction between memory instructions and
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64-bit integer multiply-accumulate instructions.
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@ -15852,99 +15874,124 @@ increases code size. Code that is sensitive to stack space usage, such
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as embedded systems and operating system kernels, may want to reduce the
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preferred alignment to @option{-mpreferred-stack-boundary=2}.
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@need 200
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@item -mmmx
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@itemx -mno-mmx
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@itemx -msse
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@itemx -mno-sse
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@itemx -msse2
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@itemx -mno-sse2
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@itemx -msse3
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@itemx -mno-sse3
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@itemx -mssse3
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@itemx -mno-ssse3
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@itemx -msse4.1
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@need 800
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@itemx -mno-sse4.1
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@itemx -msse4.2
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@itemx -mno-sse4.2
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@itemx -msse4
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@itemx -mno-sse4
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@itemx -mavx
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@itemx -mno-avx
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@itemx -mavx2
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@itemx -mno-avx2
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@itemx -mavx512f
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@itemx -mno-avx512f
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@need 800
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@itemx -mavx512pf
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@itemx -mno-avx512pf
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@itemx -mavx512er
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@itemx -mno-avx512er
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@itemx -mavx512cd
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@itemx -mno-avx512cd
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@itemx -msha
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@itemx -mno-sha
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@itemx -maes
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@itemx -mno-aes
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@itemx -mpclmul
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@itemx -mno-pclmul
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@itemx -mclfushopt
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@itemx -mno-clflsuhopt
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@need 800
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@itemx -mfsgsbase
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@itemx -mno-fsgsbase
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@itemx -mrdrnd
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@itemx -mno-rdrnd
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@itemx -mf16c
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@itemx -mno-f16c
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@itemx -mfma
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@itemx -mno-fma
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@itemx -mprefetchwt1
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@itemx -mno-prefetchwt1
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@itemx -msse4a
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@itemx -mno-sse4a
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@itemx -mfma4
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@itemx -mno-fma4
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@need 800
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||||
@itemx -mxop
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@itemx -mno-xop
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@itemx -mlwp
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@itemx -mno-lwp
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||||
@itemx -m3dnow
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||||
@itemx -mno-3dnow
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@itemx -mpopcnt
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||||
@itemx -mno-popcnt
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||||
@itemx -mabm
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||||
@itemx -mno-abm
|
||||
@itemx -mbmi
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||||
@itemx -mbmi2
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||||
@itemx -mno-bmi
|
||||
@itemx -mno-bmi2
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||||
@itemx -mlzcnt
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@itemx -mno-lzcnt
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@itemx -mfxsr
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@itemx -mxsave
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@itemx -mxsaveopt
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||||
@itemx -mrtm
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@itemx -mtbm
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||||
@itemx -mno-tbm
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@itemx -mxsavec
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||||
@itemx -mno-xsavec
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||||
@itemx -mxsaves
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@itemx -mno-xsaves
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@itemx -mmpx
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||||
@itemx -mno-mpx
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@opindex mmmx
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@opindex mno-mmx
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@need 200
|
||||
@itemx -msse
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@opindex msse
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||||
@opindex mno-sse
|
||||
@need 200
|
||||
@itemx -msse2
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||||
@need 200
|
||||
@itemx -msse3
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||||
@need 200
|
||||
@itemx -mssse3
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||||
@need 200
|
||||
@itemx -msse4
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||||
@need 200
|
||||
@itemx -msse4a
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@need 200
|
||||
@itemx -msse4.1
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||||
@need 200
|
||||
@itemx -msse4.2
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||||
@need 200
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@itemx -mavx
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@opindex mavx
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@need 200
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||||
@itemx -mavx2
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@need 200
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@itemx -mavx512f
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@need 200
|
||||
@itemx -mavx512pf
|
||||
@need 200
|
||||
@itemx -mavx512er
|
||||
@need 200
|
||||
@itemx -mavx512cd
|
||||
@need 200
|
||||
@itemx -msha
|
||||
@opindex msha
|
||||
@need 200
|
||||
@itemx -maes
|
||||
@opindex maes
|
||||
@need 200
|
||||
@itemx -mpclmul
|
||||
@opindex mpclmul
|
||||
@need 200
|
||||
@itemx -mclfushopt
|
||||
@opindex mclfushopt
|
||||
@need 200
|
||||
@itemx -mfsgsbase
|
||||
@opindex mfsgsbase
|
||||
@need 200
|
||||
@itemx -mrdrnd
|
||||
@opindex mrdrnd
|
||||
@need 200
|
||||
@itemx -mf16c
|
||||
@opindex mf16c
|
||||
@need 200
|
||||
@itemx -mfma
|
||||
@opindex mfma
|
||||
@need 200
|
||||
@itemx -mfma4
|
||||
@need 200
|
||||
@itemx -mno-fma4
|
||||
@need 200
|
||||
@itemx -mprefetchwt1
|
||||
@opindex mprefetchwt1
|
||||
@need 200
|
||||
@itemx -mxop
|
||||
@opindex mxop
|
||||
@need 200
|
||||
@itemx -mlwp
|
||||
@opindex mlwp
|
||||
@need 200
|
||||
@itemx -m3dnow
|
||||
@opindex m3dnow
|
||||
@opindex mno-3dnow
|
||||
These switches enable or disable the use of instructions in the MMX, SSE,
|
||||
@need 200
|
||||
@itemx -mpopcnt
|
||||
@opindex mpopcnt
|
||||
@need 200
|
||||
@itemx -mabm
|
||||
@opindex mabm
|
||||
@need 200
|
||||
@itemx -mbmi
|
||||
@opindex mbmi
|
||||
@need 200
|
||||
@itemx -mbmi2
|
||||
@need 200
|
||||
@itemx -mlzcnt
|
||||
@opindex mlzcnt
|
||||
@need 200
|
||||
@itemx -mfxsr
|
||||
@opindex mfxsr
|
||||
@need 200
|
||||
@itemx -mxsave
|
||||
@opindex mxsave
|
||||
@need 200
|
||||
@itemx -mxsaveopt
|
||||
@opindex mxsaveopt
|
||||
@need 200
|
||||
@itemx -mxsavec
|
||||
@opindex mxsavec
|
||||
@need 200
|
||||
@itemx -mxsaves
|
||||
@opindex mxsaves
|
||||
@need 200
|
||||
@itemx -mrtm
|
||||
@opindex mrtm
|
||||
@need 200
|
||||
@itemx -mtbm
|
||||
@opindex mtbm
|
||||
@need 200
|
||||
@itemx -mmpx
|
||||
@opindex mmpx
|
||||
These switches enable the use of instructions in the MMX, SSE,
|
||||
SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
|
||||
SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
|
||||
BMI, BMI2, FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, MPX or 3DNow!@:
|
||||
extended instruction sets.
|
||||
extended instruction sets. Each has a corresponding @option{-mno-} option
|
||||
to disable use of these instructions.
|
||||
|
||||
These extensions are also available as built-in functions: see
|
||||
@ref{X86 Built-in Functions}, for details of the functions enabled and
|
||||
disabled by these switches.
|
||||
|
|
@ -16288,7 +16335,7 @@ those issues, regardless the RAX register value.
|
|||
|
||||
@item -m8bit-idiv
|
||||
@itemx -mno-8bit-idiv
|
||||
@opindex 8bit-idiv
|
||||
@opindex m8bit-idiv
|
||||
On some processors, like Intel Atom, 8-bit unsigned integer divide is
|
||||
much faster than 32-bit/64-bit integer divide. This option generates a
|
||||
run-time check. If both dividend and divisor are within range of 0
|
||||
|
|
@ -16297,8 +16344,8 @@ to 255, 8-bit unsigned integer divide is used instead of
|
|||
|
||||
@item -mavx256-split-unaligned-load
|
||||
@itemx -mavx256-split-unaligned-store
|
||||
@opindex avx256-split-unaligned-load
|
||||
@opindex avx256-split-unaligned-store
|
||||
@opindex mavx256-split-unaligned-load
|
||||
@opindex mavx256-split-unaligned-store
|
||||
Split 32-byte AVX unaligned load and store.
|
||||
|
||||
@item -mstack-protector-guard=@var{guard}
|
||||
|
|
@ -18910,7 +18957,7 @@ cause the linker to search for a script called @file{xxx.ld}.
|
|||
This option is also passed on to the assembler.
|
||||
|
||||
@item -mcpu=
|
||||
@opindex -mcpu=
|
||||
@opindex mcpu=
|
||||
Specifies the ISA to use. Accepted values are @code{msp430},
|
||||
@code{msp430x} and @code{msp430xv2}. This option is deprecated. The
|
||||
@option{-mmcu=} option should be used to select the ISA.
|
||||
|
|
@ -20684,7 +20731,7 @@ values, however, so the FPU hardware is not used for doubles if the
|
|||
This is because the RX FPU instructions are themselves unsafe.
|
||||
|
||||
@item -mcpu=@var{name}
|
||||
@opindex -mcpu
|
||||
@opindex mcpu
|
||||
Selects the type of RX CPU to be targeted. Currently three types are
|
||||
supported, the generic @var{RX600} and @var{RX200} series hardware and
|
||||
the specific @var{RX610} CPU. The default is @var{RX600}.
|
||||
|
|
@ -22566,7 +22613,7 @@ routine for the debugger.
|
|||
Default to 64-bit memory allocation routines.
|
||||
|
||||
@item -mpointer-size=@var{size}
|
||||
@opindex -mpointer-size=@var{size}
|
||||
@opindex mpointer-size=@var{size}
|
||||
Set the default size of pointers. Possible options for @var{size} are
|
||||
@samp{32} or @samp{short} for 32 bit pointers, @samp{64} or @samp{long}
|
||||
for 64 bit pointers, and @samp{no} for supporting only 32 bit pointers.
|
||||
|
|
|
|||
Loading…
Reference in New Issue