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Enable AES, PCLMUL and RDRND for Silvermont 

gcc/

2013-11-22  Yuri Rumyantsev  <ysrumyan@gmail.com>

	* config/i386/i386.c(processor_alias_table): Enable PTA_AES,
	PTA_PCLMUL and PTA_RDRND for Silvermont.
	* config/i386/driver-i386.c (host_detect_local_cpu): Set up cpu
	for Silvermont.

	* doc/invoke.texi: Mention AES, PCLMUL and RDRND for Silvermont.

libgcc/

2013-11-22  Yuri Rumyantsev  <ysrumyan@gmail.com>

	 * config/i386/cpuinfo.c (get_intel_cpu): Add Silvermont cases.

From-SVN: r205275
This commit is contained in:
Yuri Rumyantsev 2013-11-22 16:33:40 +00:00 committed by H.J. Lu
parent 861c1d8ed5
commit e52876717c
6 changed files with 26 additions and 3 deletions
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9
gcc/ChangeLog
View File

@ -1,3 +1,12 @@
2013-11-22 Yuri Rumyantsev <ysrumyan@gmail.com>
* config/i386/i386.c(processor_alias_table): Enable PTA_AES,
PTA_PCLMUL and PTA_RDRND for Silvermont.
* config/i386/driver-i386.c (host_detect_local_cpu): Set up cpu
for Silvermont.
* doc/invoke.texi: Mention AES, PCLMUL and RDRND for Silvermont.
2013-11-22 Andrew MacLeod <amacleod@redhat.com>
* hooks.h (hook_uint_mode_0): Add Prototype.

5
gcc/config/i386/driver-i386.c
View File

@ -646,6 +646,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
/* Atom. */
cpu = "atom";
break;
case 0x37:
case 0x4d:
/* Silvermont. */
cpu = "slm";
break;
case 0x0f:
/* Merom. */
case 0x17:

4
gcc/config/i386/i386.c
View File

@ -3147,8 +3147,8 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSSE3 | PTA_CX16 | PTA_MOVBE | PTA_FXSR},
{"slm", PROCESSOR_SLM, CPU_SLM,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_MOVBE
| PTA_FXSR},
| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
| PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
{"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},

2
gcc/doc/invoke.texi
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@ -14535,7 +14535,7 @@ instruction set support.
@item slm
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2 and POPCNT instruction set support.
SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
@item k6
AMD K6 CPU with MMX instruction set support.

4
libgcc/ChangeLog
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@ -1,3 +1,7 @@
2013-11-22 Yuri Rumyantsev <ysrumyan@gmail.com>
* config/i386/cpuinfo.c (get_intel_cpu): Add Silvermont cases.
2013-11-18 Jan Hubicka <jh@suse.cz>
* libgcov-driver.c (run_accounted): Make global level static.

5
libgcc/config/i386/cpuinfo.c
View File

@ -170,6 +170,11 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
/* Atom. */
__cpu_model.__cpu_type = INTEL_ATOM;
break;
case 0x37:
case 0x4d:
/* Silvermont. */
__cpu_model.__cpu_type = INTEL_SLM;
break;
case 0x1a:
case 0x1e:
case 0x1f: