mirror of git://gcc.gnu.org/git/gcc.git
aarch64-simd.md (aarch64_simd_vec_set<mode>): Adjust for big-endian element order.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com> * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Adjust for big-endian element order. (aarch64_simd_vec_setv2di): Likewise. (*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>, *aarch64_get_lane_zero_extendsi<mode>, aarch64_get_lane): Likewise. (vec_extract): Expand using aarch64_get_lane. * config/aarch64/aarch64.h (ENDIAN_LANE_N): New. From-SVN: r205267
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Tejas Belagod
Tejas Belagod
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635ad37e5a
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@ -1,3 +1,13 @@
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2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Adjust
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for big-endian element order.
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(aarch64_simd_vec_setv2di): Likewise.
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(*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>,
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*aarch64_get_lane_zero_extendsi<mode>, aarch64_get_lane): Likewise.
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(vec_extract): Expand using aarch64_get_lane.
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* config/aarch64/aarch64.h (ENDIAN_LANE_N): New.
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2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
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* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads
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@ -428,9 +428,19 @@
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(match_operand:VQ_S 3 "register_operand" "0,0")
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(match_operand:SI 2 "immediate_operand" "i,i")))]
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"TARGET_SIMD"
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"@
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ins\t%0.<Vetype>[%p2], %w1
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ins\\t%0.<Vetype>[%p2], %1.<Vetype>[0]"
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{
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int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
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operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt);
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switch (which_alternative)
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{
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case 0:
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return "ins\\t%0.<Vetype>[%p2], %w1";
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case 1:
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return "ins\\t%0.<Vetype>[%p2], %1.<Vetype>[0]";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "neon_from_gp<q>, neon_ins<q>")]
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)
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@ -692,9 +702,19 @@
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(match_operand:V2DI 3 "register_operand" "0,0")
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(match_operand:SI 2 "immediate_operand" "i,i")))]
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"TARGET_SIMD"
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"@
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ins\t%0.d[%p2], %1
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ins\\t%0.d[%p2], %1.d[0]"
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{
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int elt = ENDIAN_LANE_N (V2DImode, exact_log2 (INTVAL (operands[2])));
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operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt);
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switch (which_alternative)
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{
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case 0:
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return "ins\\t%0.d[%p2], %1";
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case 1:
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return "ins\\t%0.d[%p2], %1.d[0]";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "neon_from_gp, neon_ins_q")]
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)
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@ -719,7 +739,12 @@
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(match_operand:VDQF 3 "register_operand" "0")
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(match_operand:SI 2 "immediate_operand" "i")))]
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"TARGET_SIMD"
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"ins\t%0.<Vetype>[%p2], %1.<Vetype>[0]";
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{
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int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2])));
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operands[2] = GEN_INT ((HOST_WIDE_INT)1 << elt);
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return "ins\t%0.<Vetype>[%p2], %1.<Vetype>[0]";
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}
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[(set_attr "type" "neon_ins<q>")]
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)
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@ -2022,7 +2047,10 @@
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(match_operand:VDQQH 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
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"TARGET_SIMD"
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"smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "smov\\t%<GPI:w>0, %1.<VDQQH:Vetype>[%2]";
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}
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[(set_attr "type" "neon_to_gp<q>")]
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)
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@ -2033,22 +2061,36 @@
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(match_operand:VDQQH 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
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"TARGET_SIMD"
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"umov\\t%w0, %1.<Vetype>[%2]"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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return "umov\\t%w0, %1.<Vetype>[%2]";
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}
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[(set_attr "type" "neon_to_gp<q>")]
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)
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;; Lane extraction of a value, neither sign nor zero extension
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;; is guaranteed so upper bits should be considered undefined.
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(define_insn "aarch64_get_lane<mode>"
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[(set (match_operand:<VEL> 0 "register_operand" "=r, w")
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[(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=r, w, Utv")
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(vec_select:<VEL>
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(match_operand:VALL 1 "register_operand" "w, w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i, i")])))]
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(match_operand:VALL 1 "register_operand" "w, w, w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i, i, i")])))]
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"TARGET_SIMD"
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"@
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umov\\t%<vwcore>0, %1.<Vetype>[%2]
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dup\\t%<Vetype>0, %1.<Vetype>[%2]"
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[(set_attr "type" "neon_to_gp<q>, neon_dup<q>")]
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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switch (which_alternative)
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{
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case 0:
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return "umov\\t%<vwcore>0, %1.<Vetype>[%2]";
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case 1:
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return "dup\\t%<Vetype>0, %1.<Vetype>[%2]";
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case 2:
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return "st1\\t{%1.<Vetype>}[%2], %0";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")]
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)
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(define_expand "aarch64_get_lanedi"
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@ -4028,16 +4070,13 @@
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;; Standard pattern name vec_extract<mode>.
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(define_insn "vec_extract<mode>"
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[(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=r, w, Utv")
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(vec_select:<VEL>
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(match_operand:VALL 1 "register_operand" "w, w, w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i,i,i")])))]
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(define_expand "vec_extract<mode>"
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[(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "")
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(match_operand:VALL 1 "register_operand" "")
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(match_operand:SI 2 "immediate_operand" "")]
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"TARGET_SIMD"
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"@
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umov\\t%<vw>0, %1.<Vetype>[%2]
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dup\\t%<Vetype>0, %1.<Vetype>[%2]
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st1\\t{%1.<Vetype>}[%2], %0"
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[(set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>")]
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)
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{
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emit_insn
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(gen_aarch64_get_lane<mode> (operands[0], operands[1], operands[2]));
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DONE;
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})
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@ -854,4 +854,7 @@ extern enum aarch64_code_model aarch64_cmodel;
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((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
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|| (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode)
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#define ENDIAN_LANE_N(mode, n) \
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(BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
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#endif /* GCC_AARCH64_H */
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