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2017-06-07 Tamar Christina <tamar.christina@arm.com> 

* config/aarch64/aarch64.md
        (copysignsf3): Fix mask generation.

From-SVN: r248949
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Tamar Christina 2017-06-07 09:36:17 +00:00 committed by Tamar Christina
parent 6eb2ac659c
commit eb1d2d5d99
2 changed files with 11 additions and 4 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2017-06-07 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.md
(copysignsf3): Fix mask generation.
2017-06-07 Jakub Jelinek <jakub@redhat.com> 2017-06-07 Jakub Jelinek <jakub@redhat.com>
* dumpfile.h (enum tree_dump_index): Rename TDI_generic to * dumpfile.h (enum tree_dump_index): Rename TDI_generic to

10
gcc/config/aarch64/aarch64.md
View File

@ -4973,14 +4973,16 @@
(match_operand:SF 2 "register_operand")] (match_operand:SF 2 "register_operand")]
"TARGET_FLOAT && TARGET_SIMD" "TARGET_FLOAT && TARGET_SIMD"
{ {
rtx mask = gen_reg_rtx (DImode); rtx v_bitmask = gen_reg_rtx (V2SImode);
/* Juggle modes to get us in to a vector mode for BSL. */ /* Juggle modes to get us in to a vector mode for BSL. */
rtx op1 = lowpart_subreg (V2SFmode, operands[1], SFmode); rtx op1 = lowpart_subreg (DImode, operands[1], SFmode);
rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode); rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode);
rtx tmp = gen_reg_rtx (V2SFmode); rtx tmp = gen_reg_rtx (V2SFmode);
emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 31)); emit_move_insn (v_bitmask,
emit_insn (gen_aarch64_simd_bslv2sf (tmp, mask, op2, op1)); aarch64_simd_gen_const_vector_dup (V2SImode,
HOST_WIDE_INT_M1U << 31));
emit_insn (gen_aarch64_simd_bslv2sf (tmp, v_bitmask, op2, op1));
emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode)); emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode));
DONE; DONE;
} }