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The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 doesn't support RSC with an immediate. 

The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2
doesn't support RSC with an immediate.  We can however emulate RSC with
zero using a shifted SBC.  If we add this to subsi3_carryin the negdi
patterns can be merged, simplifying things a bit.  This should generate
identical code in all cases.

    gcc/
        * config/arm/arm.md (subsi3_carryin): Add Thumb-2 RSC #0.
        (arm_negdi2) Rename to negdi2_insn, allow on Thumb-2.
        * config/arm/thumb2.md (thumb2_negdi2): Remove pattern.

From-SVN: r243745
This commit is contained in:
Wilco Dijkstra 2016-12-16 13:14:46 +00:00 committed by Wilco Dijkstra
parent c67b6f2683
commit ed2def05fe
3 changed files with 18 additions and 36 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2016-12-16 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (subsi3_carryin): Add Thumb-2 RSC #0.
(arm_negdi2) Rename to negdi2_insn, allow on Thumb-2.
* config/arm/thumb2.md (thumb2_negdi2): Remove pattern.
2016-12-16 Wilco Dijkstra <wdijkstr@arm.com> 2016-12-16 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14. * config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14.

22
gcc/config/arm/arm.md
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@ -1129,19 +1129,20 @@
) )
(define_insn "*subsi3_carryin" (define_insn "*subsi3_carryin"
[(set (match_operand:SI 0 "s_register_operand" "=r,r") [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I") (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I,Pz")
(match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:SI 2 "s_register_operand" "r,r,r"))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
"TARGET_32BIT" "TARGET_32BIT"
"@ "@
sbc%?\\t%0, %1, %2 sbc%?\\t%0, %1, %2
rsc%?\\t%0, %2, %1" rsc%?\\t%0, %2, %1
sbc%?\\t%0, %2, %2, lsl #1"
[(set_attr "conds" "use") [(set_attr "conds" "use")
(set_attr "arch" "*,a") (set_attr "arch" "*,a,t2")
(set_attr "predicable" "yes") (set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no") (set_attr "predicable_short_it" "no")
(set_attr "type" "adc_reg,adc_imm")] (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
) )
(define_insn "*subsi3_carryin_const" (define_insn "*subsi3_carryin_const"
@ -4681,12 +4682,13 @@
;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
;; The first alternative allows the common case of a *full* overlap. ;; The first alternative allows the common case of a *full* overlap.
(define_insn_and_split "*arm_negdi2" (define_insn_and_split "*negdi2_insn"
[(set (match_operand:DI 0 "s_register_operand" "=r,&r") [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
(neg:DI (match_operand:DI 1 "s_register_operand" "0,r"))) (neg:DI (match_operand:DI 1 "s_register_operand" "0,r")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_ARM" "TARGET_32BIT"
"#" ; "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0" "#" ; rsbs %Q0, %Q1, #0; rsc %R0, %R1, #0 (ARM)
; negs %Q0, %Q1 ; sbc %R0, %R1, %R1, lsl #1 (Thumb-2)
"&& reload_completed" "&& reload_completed"
[(parallel [(set (reg:CC CC_REGNUM) [(parallel [(set (reg:CC CC_REGNUM)
(compare:CC (const_int 0) (match_dup 1))) (compare:CC (const_int 0) (match_dup 1)))

26
gcc/config/arm/thumb2.md
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@ -125,32 +125,6 @@
(set_attr "type" "multiple")] (set_attr "type" "multiple")]
) )
;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
(define_insn_and_split "*thumb2_negdi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
(neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2"
"#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1
"&& reload_completed"
[(parallel [(set (reg:CC CC_REGNUM)
(compare:CC (const_int 0) (match_dup 1)))
(set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
(set (match_dup 2) (minus:SI (minus:SI (match_dup 3)
(ashift:SI (match_dup 3)
(const_int 1)))
(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
{
operands[2] = gen_highpart (SImode, operands[0]);
operands[0] = gen_lowpart (SImode, operands[0]);
operands[3] = gen_highpart (SImode, operands[1]);
operands[1] = gen_lowpart (SImode, operands[1]);
}
[(set_attr "conds" "clob")
(set_attr "length" "8")
(set_attr "type" "multiple")]
)
(define_insn_and_split "*thumb2_abssi2" (define_insn_and_split "*thumb2_abssi2"
[(set (match_operand:SI 0 "s_register_operand" "=&r,l,r") [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
(abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))) (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))