mirror of git://gcc.gnu.org/git/gcc.git
re PR rtl-optimization/58968 (Powerpc -mlra cannot compile ormas1.f in gamess Spec 2006 with -m32 -mcpu=power7 -O3 -mlra -w -ffast-math -funroll-loops)
2013-11-04 Vladimir Makarov <vmakarov@redhat.com> PR rtl-optimization/58968 * lra-spills.c (return_regno_p): New function. (lra_final_code_change): Use it. 2013-11-04 Vladimir Makarov <vmakarov@redhat.com> PR rtl-optimization/58968 * gfortran.dg/pr58968.f: New From-SVN: r204353
This commit is contained in:
Vladimir Makarov
Vladimir Makarov
parent
55a7f02f06
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efaf512c94
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@ -1,3 +1,9 @@
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2013-11-04 Vladimir Makarov <vmakarov@redhat.com>
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PR rtl-optimization/58968
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* lra-spills.c (return_regno_p): New function.
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(lra_final_code_change): Use it.
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2013-11-04 Joseph Myers <joseph@codesourcery.com>
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2013-11-04 Joseph Myers <joseph@codesourcery.com>
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* doc/cpp.texi (__GCC_IEC_559, __GCC_IEC_559_COMPLEX): Document
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* doc/cpp.texi (__GCC_IEC_559, __GCC_IEC_559_COMPLEX): Document
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@ -618,6 +618,33 @@ alter_subregs (rtx *loc, bool final_p)
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return res;
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return res;
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}
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}
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/* Return true if REGNO is used for return in the current
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function. */
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static bool
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return_regno_p (unsigned int regno)
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{
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rtx outgoing = crtl->return_rtx;
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if (! outgoing)
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return false;
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if (REG_P (outgoing))
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return REGNO (outgoing) == regno;
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else if (GET_CODE (outgoing) == PARALLEL)
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{
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int i;
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for (i = 0; i < XVECLEN (outgoing, 0); i++)
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{
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rtx x = XEXP (XVECEXP (outgoing, 0, i), 0);
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if (REG_P (x) && REGNO (x) == regno)
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return true;
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}
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}
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return false;
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}
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/* Final change of pseudos got hard registers into the corresponding
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/* Final change of pseudos got hard registers into the corresponding
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hard registers and removing temporary clobbers. */
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hard registers and removing temporary clobbers. */
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void
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void
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@ -625,7 +652,7 @@ lra_final_code_change (void)
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{
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{
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int i, hard_regno;
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int i, hard_regno;
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basic_block bb;
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basic_block bb;
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rtx insn, curr, set;
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rtx insn, curr;
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int max_regno = max_reg_num ();
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int max_regno = max_reg_num ();
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for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
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for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
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@ -636,7 +663,6 @@ lra_final_code_change (void)
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FOR_BB_INSNS_SAFE (bb, insn, curr)
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FOR_BB_INSNS_SAFE (bb, insn, curr)
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if (INSN_P (insn))
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if (INSN_P (insn))
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{
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{
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bool change_p;
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rtx pat = PATTERN (insn);
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rtx pat = PATTERN (insn);
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if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat))
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if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat))
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@ -649,12 +675,24 @@ lra_final_code_change (void)
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continue;
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continue;
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}
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}
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set = single_set (insn);
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/* IRA can generate move insns involving pseudos. It is
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change_p = (set != NULL
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better remove them earlier to speed up compiler a bit.
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&& REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
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It is also better to do it here as they might not pass
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&& REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
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final RTL check in LRA, (e.g. insn moving a control
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&& REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER);
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register into itself). So remove an useless move insn
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unless next insn is USE marking the return reg (we should
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save this as some subsequent optimizations assume that
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such original insns are saved). */
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if (NONJUMP_INSN_P (insn) && GET_CODE (pat) == SET
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&& REG_P (SET_SRC (pat)) && REG_P (SET_DEST (pat))
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&& REGNO (SET_SRC (pat)) == REGNO (SET_DEST (pat))
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&& ! return_regno_p (REGNO (SET_SRC (pat))))
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{
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lra_invalidate_insn_data (insn);
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delete_insn (insn);
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continue;
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}
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lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
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lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
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struct lra_static_insn_data *static_id = id->insn_static_data;
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struct lra_static_insn_data *static_id = id->insn_static_data;
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bool insn_change_p = false;
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bool insn_change_p = false;
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@ -668,20 +706,5 @@ lra_final_code_change (void)
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}
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}
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if (insn_change_p)
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if (insn_change_p)
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lra_update_operator_dups (id);
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lra_update_operator_dups (id);
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if (change_p && REGNO (SET_SRC (set)) == REGNO (SET_DEST (set)))
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{
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/* Remove an useless move insn but only involving
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pseudos as some subsequent optimizations are based on
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that move insns involving originally hard registers
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are preserved. IRA can generate move insns involving
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pseudos. It is better remove them earlier to speed
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up compiler a bit. It is also better to do it here
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as they might not pass final RTL check in LRA,
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(e.g. insn moving a control register into
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itself). */
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lra_invalidate_insn_data (insn);
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delete_insn (insn);
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}
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}
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}
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}
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}
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@ -1,3 +1,8 @@
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2013-11-04 Vladimir Makarov <vmakarov@redhat.com>
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PR rtl-optimization/58968
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* gfortran.dg/pr58968.f: New
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2013-11-04 Marek Polacek <polacek@redhat.com>
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2013-11-04 Marek Polacek <polacek@redhat.com>
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PR c++/58979
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PR c++/58979
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@ -0,0 +1,96 @@
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C PR rtl-optimization/58968.f
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C { dg-do compile { target powerpc*-*-*} }
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C { dg-options "-mcpu=power7 -O3 -w -ffast-math -funroll-loops" }
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SUBROUTINE MAKTABS(IW,SOME,LBOX1,LBOX2,LBOX3,NSPACE,NA,NB,
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* LBST,X,
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* NX,IAMA,IAMI,IBMA,IBMI,MNUM,IDIM,MSTA,IBO,
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* IDSYM,ISYM1,NSYM,
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* NACT,LWRK,KTAB,LGMUL,
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* LCON,LCOA,LCOB,
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* LANDET,LBNDET,NAST,NBST,LSYMA,LSYMB,LGCOM,
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* MINI,MAXI,LSPA,LSPB,LDISB,
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* LSAS,LSBS,LSAC,LSBC,
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* ITGA,ITGB,IAST,IBST,NCI,NA1EX,NB1EX,FDIRCT)
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IMPLICIT DOUBLE PRECISION(A-H,O-Z)
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LOGICAL SOME
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DIMENSION LBOX1(NSPACE),LBOX2(NSPACE),LBOX3(NSPACE),LBST(NSPACE)
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DIMENSION X(NX)
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DIMENSION IAMA(NSPACE),IAMI(NSPACE),IBMA(NSPACE),IBMI(NSPACE)
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DIMENSION MNUM(NSPACE),IDIM(NSPACE),MSTA(NSPACE+1),IBO(NACT)
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DIMENSION LWRK(43),KTAB(NSYM),LGMUL(NSYM,NSYM)
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DIMENSION LCON(NA)
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DIMENSION LCOA(NSYM,ITGA),LCOB(NSYM,ITGB)
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DIMENSION LANDET(NSPACE,ITGA),LBNDET(NSPACE,ITGB)
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DIMENSION NAST(ITGA+1),NBST(ITGB+1)
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DIMENSION LSYMA(IAST),LSYMB(IBST)
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DIMENSION LGCOM(ITGB,ITGA)
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DIMENSION MINI(NSPACE),MAXI(NSPACE)
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DIMENSION LSPA(IAST),LSPB(IBST)
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DIMENSION LDISB(NSYM,ITGB,ITGA)
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DIMENSION LSAS(NSYM+1,ITGA),LSBS(NSYM+1,ITGB)
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DIMENSION LSAC(IAST),LSBC(IBST)
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LOGICAL FDIRCT
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LCOA = 0
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LCOB = 0
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ISTA1 = LBST(1)
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CALL RESETCO(LBOX1,NSPACE,NB,IBMA,IBMI,LBOX2)
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NAST(1) = 0
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NBST(1) = 0
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DO II=1,ITGA
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ITOT = 1
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DO JJ=1,NSPACE
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ITOT = ITOT * LANDET(JJ,II)
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ENDDO
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NAST(II+1) = NAST(II) + ITOT
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ENDDO
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DO II=1,ITGB
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ITOT = 1
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DO JJ=1,NSPACE
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ITOT = ITOT * LBNDET(JJ,II)
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ENDDO
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NBST(II+1) = NBST(II) + ITOT
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ENDDO
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ICOMP = 0
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CALL RESETCO(LBOX1,NSPACE,NA,IAMA,IAMI,LBOX3)
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NA1EX = 0
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NB1EX = 0
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CALL RESETCO(LBOX1,NSPACE,NB,IBMA,IBMI,LBOX3)
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DO IIB = 1,ITGB
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CALL RESETDE(LBOX1,NSPACE,NB,MSTA,LCON)
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DO KKB=NBST(IIB)+1,NBST(IIB+1)
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DO II=1,NSPACE
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LBOX2(II) = LBOX1(II)
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ENDDO
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IEBS = NB+1
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DO ISPB1=NSPACE,1,-1
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IOC1 = LBOX1(ISPB1)
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IEBE = IEBS - 1
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IEBS = IEBS - IOC1
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LBOX2(ISPB1) = LBOX2(ISPB1)-1
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DO IB1=IEBE,IEBS,-1
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IO1 = LCON(IB1)
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IGBE = IEBE - LBOX1(ISPB1)
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DO ISPB2=ISPB1,NSPACE
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IGBS = IGBE + 1
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IGBE = IGBE + LBOX1(ISPB2)
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LBOX2(ISPB2) = LBOX2(ISPB2) + 1
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IGBA = MAX(IB1+1,IGBS)
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DO IGAP=IGBA,IGBE+1
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DO JJ=ISTA,IEND
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NB1EX = NB1EX + 1
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ENDDO
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ISTA = LCON(IGAP)+1
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IEND = LCON(IGAP+1)-1
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IF (IGAP.EQ.IGBE) IEND=MSTA(ISPB2+1)-1
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ENDDO
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LBOX2(ISPB2) = LBOX2(ISPB2) - 1
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ENDDO
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ENDDO
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LBOX2(ISPB1) = LBOX2(ISPB1) + 1
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ENDDO
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CALL MOVEUP2(LBOX1,NSPACE,NB,MSTA,LCON)
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ENDDO
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CALL PUSHCO(LBOX1,NSPACE,NB,IBMA,IBMI,LBOX3,IEND)
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ENDDO
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RETURN
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END
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