mirror of git://gcc.gnu.org/git/gcc.git
s390.md ("*brx_stage1_<GPR:mode>", [...]): New patterns.
2009-08-20 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("*brx_stage1_<GPR:mode>", "*brxg_64bit",
"*brx_64bit", "*brx_31bit"): New patterns.
* config/s390/s390.c ('E'): New output modifier.
From-SVN: r150954
This commit is contained in:
Andreas Krebbel
Andreas Krebbel
parent
a552b644fb
commit
f114923514
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@ -1,3 +1,9 @@
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2009-08-20 Andreas Krebbel <krebbel1@de.ibm.com>
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* config/s390/s390.md ("*brx_stage1_<GPR:mode>", "*brxg_64bit",
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"*brx_64bit", "*brx_31bit"): New patterns.
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* config/s390/s390.c ('E'): New output modifier.
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2009-08-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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Richard Earnshaw <richard.earnshaw@arm.com>
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@ -197,6 +197,9 @@
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(define_predicate "s390_scond_operator"
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(match_code "ltu, gtu, leu, geu"))
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(define_predicate "s390_brx_operator"
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(match_code "le, gt"))
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;; Return nonzero if OP is a valid comparison operator
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;; for an ALC condition.
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@ -4957,6 +4957,7 @@ print_operand_address (FILE *file, rtx addr)
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'C': print opcode suffix for branch condition.
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'D': print opcode suffix for inverse branch condition.
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'E': print opcode suffix for branch on index instruction.
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'J': print tls_load/tls_gdcall/tls_ldcall suffix
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'G': print the size of the operand in bytes.
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'O': print only the displacement of a memory reference.
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@ -4989,6 +4990,15 @@ print_operand (FILE *file, rtx x, int code)
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fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
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return;
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case 'E':
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if (GET_CODE (x) == LE)
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fprintf (file, "l");
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else if (GET_CODE (x) == GT)
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fprintf (file, "h");
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else
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gcc_unreachable ();
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return;
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case 'J':
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if (GET_CODE (x) == SYMBOL_REF)
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{
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@ -7561,6 +7561,180 @@
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;; This is all complicated by the fact that since this is a jump insn
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;; we must handle our own output reloads.
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;; branch on index
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; This splitter will be matched by combine and has to add the 2 moves
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; necessary to load the compare and the increment values into a
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; register pair as needed by brxle.
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(define_insn_and_split "*brx_stage1_<GPR:mode>"
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[(set (pc)
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(if_then_else
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(match_operator 6 "s390_brx_operator"
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[(plus:GPR (match_operand:GPR 1 "register_operand" "")
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(match_operand:GPR 2 "general_operand" ""))
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(match_operand:GPR 3 "register_operand" "")])
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(set (match_operand:GPR 4 "nonimmediate_operand" "")
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(plus:GPR (match_dup 1) (match_dup 2)))
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(clobber (match_scratch:GPR 5 ""))]
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"TARGET_CPU_ZARCH"
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"#"
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"!reload_completed && !reload_in_progress"
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[(set (match_dup 7) (match_dup 2)) ; the increment
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(set (match_dup 8) (match_dup 3)) ; the comparison value
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(parallel [(set (pc)
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(if_then_else
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(match_op_dup 6
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[(plus:GPR (match_dup 1) (match_dup 7))
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(match_dup 8)])
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(label_ref (match_dup 0))
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(pc)))
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(set (match_dup 4)
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(plus:GPR (match_dup 1) (match_dup 7)))
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(clobber (match_dup 5))
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(clobber (reg:CC CC_REGNUM))])]
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{
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rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
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operands[7] = gen_lowpart (<GPR:MODE>mode,
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gen_highpart (word_mode, dreg));
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operands[8] = gen_lowpart (<GPR:MODE>mode,
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gen_lowpart (word_mode, dreg));
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})
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; brxlg, brxhg
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(define_insn_and_split "*brxg_64bit"
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[(set (pc)
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(if_then_else
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(match_operator 5 "s390_brx_operator"
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[(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
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(subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
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(subreg:DI (match_dup 2) 8)])
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
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(plus:DI (match_dup 1)
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(subreg:DI (match_dup 2) 0)))
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(clobber (match_scratch:DI 4 "=X,&1,&?d"))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_64BIT"
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{
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if (which_alternative != 0)
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return "#";
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else if (get_attr_length (insn) == 6)
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return "brx%E5g\t%1,%2,%l0";
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else
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return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
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}
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"&& reload_completed
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&& (!REG_P (operands[3])
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|| !rtx_equal_p (operands[1], operands[3]))"
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[(set (match_dup 4) (match_dup 1))
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(parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
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(clobber (reg:CC CC_REGNUM))])
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(set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
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(set (match_dup 3) (match_dup 4))
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(set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
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(label_ref (match_dup 0))
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(pc)))]
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""
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[(set_attr "op_type" "RIE")
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(set_attr "type" "branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
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(const_int 6) (const_int 16)))])
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; brxle, brxh
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(define_insn_and_split "*brx_64bit"
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[(set (pc)
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(if_then_else
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(match_operator 5 "s390_brx_operator"
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[(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
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(subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
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(subreg:SI (match_dup 2) 12)])
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
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(plus:SI (match_dup 1)
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(subreg:SI (match_dup 2) 4)))
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(clobber (match_scratch:SI 4 "=X,&1,&?d"))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_64BIT"
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{
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if (which_alternative != 0)
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return "#";
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else if (get_attr_length (insn) == 6)
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return "brx%C5\t%1,%2,%l0";
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else
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return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
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}
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"&& reload_completed
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&& (!REG_P (operands[3])
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|| !rtx_equal_p (operands[1], operands[3]))"
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[(set (match_dup 4) (match_dup 1))
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(parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
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(clobber (reg:CC CC_REGNUM))])
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(set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
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(set (match_dup 3) (match_dup 4))
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(set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
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(label_ref (match_dup 0))
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(pc)))]
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""
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[(set_attr "op_type" "RSI")
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(set_attr "type" "branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
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(const_int 6) (const_int 14)))])
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; brxle, brxh
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(define_insn_and_split "*brx_31bit"
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[(set (pc)
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(if_then_else
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(match_operator 5 "s390_brx_operator"
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[(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
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(subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
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(subreg:SI (match_dup 2) 4)])
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(label_ref (match_operand 0 "" ""))
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(pc)))
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(set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
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(plus:SI (match_dup 1)
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(subreg:SI (match_dup 2) 0)))
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(clobber (match_scratch:SI 4 "=X,&1,&?d"))
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(clobber (reg:CC CC_REGNUM))]
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"!TARGET_64BIT && TARGET_CPU_ZARCH"
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{
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if (which_alternative != 0)
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return "#";
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else if (get_attr_length (insn) == 6)
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return "brx%C5\t%1,%2,%l0";
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else
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return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
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}
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"&& reload_completed
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&& (!REG_P (operands[3])
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|| !rtx_equal_p (operands[1], operands[3]))"
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[(set (match_dup 4) (match_dup 1))
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(parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
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(clobber (reg:CC CC_REGNUM))])
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(set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
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(set (match_dup 3) (match_dup 4))
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(set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
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(label_ref (match_dup 0))
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(pc)))]
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""
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[(set_attr "op_type" "RSI")
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(set_attr "type" "branch")
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(set (attr "length")
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(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
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(const_int 6) (const_int 14)))])
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;; branch on count
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(define_expand "doloop_end"
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[(use (match_operand 0 "" "")) ; loop pseudo
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(use (match_operand 1 "" "")) ; iterations; zero if unknown
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