mirror of git://gcc.gnu.org/git/gcc.git
configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9.
* configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9. * config/sparc/cacheline.h: New file. * config/sparc/target.h: Likewise. * config/sparc/sjlj.S: Likewise. * config/linux/sparc/futex_bits.h: Likewise. From-SVN: r184177
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
255a9a1bb5
commit
f3f5e3c32e
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@ -1,4 +1,12 @@
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2012-02-11 Eric Botcazou <ebotcazou@adacore.com>
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2012-02-13 Eric Botcazou <ebotcazou@adacore.com>
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* configure.tgt (target_cpu): Handle sparc and sparc64 & sparcv9.
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* config/sparc/cacheline.h: New file.
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* config/sparc/target.h: Likewise.
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* config/sparc/sjlj.S: Likewise.
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* config/linux/sparc/futex_bits.h: Likewise.
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2012-02-13 Eric Botcazou <ebotcazou@adacore.com>
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* configure.ac (link_itm): Fix comment.
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* configure.ac (link_itm): Fix comment.
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* configure: Regenerate.
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* configure: Regenerate.
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@ -0,0 +1,62 @@
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/* Copyright (C) 2012 Free Software Foundation, Inc.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sys/syscall.h>
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static inline long
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sys_futex0 (std::atomic<int> *addr, int op, int val)
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{
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register long int g1 __asm__ ("g1");
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register long int o0 __asm__ ("o0");
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register long int o1 __asm__ ("o1");
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register long int o2 __asm__ ("o2");
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register long int o3 __asm__ ("o3");
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long res;
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g1 = SYS_futex;
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o0 = (long) addr;
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o1 = op;
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o2 = val;
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o3 = 0;
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#ifdef __arch64__
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__asm volatile ("ta 0x6d"
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#else
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__asm volatile ("ta 0x10"
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#endif
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: "=r"(g1), "=r"(o0)
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: "0"(g1), "1"(o0), "r"(o1), "r"(o2), "r"(o3)
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: "g2", "g3", "g4", "g5", "g6",
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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"f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
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"f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
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"cc", "memory");
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res = o0;
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if (__builtin_expect ((unsigned long) res >= -515UL, 0))
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res =- res;
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return res;
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}
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@ -0,0 +1,41 @@
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/* Copyright (C) 2012 Free Software Foundation, Inc.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef LIBITM_SPARC_CACHELINE_H
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#define LIBITM_SPARC_CACHELINE_H 1
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// A cacheline is the smallest unit with which locks are associated.
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// The current implementation of the _ITM_[RW] barriers assumes that
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// all data types can fit (aligned) within a cachline, which means
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// in practice sizeof(complex long double) is the smallest cacheline size.
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// It ought to be small enough for efficient manipulation of the
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// modification mask, below.
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#ifdef __arch64__
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# define CACHELINE_SIZE 64
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#else
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# define CACHELINE_SIZE 32
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#endif
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#include "config/generic/cacheline.h"
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#endif // LIBITM_SPARC_CACHELINE_H
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@ -0,0 +1,96 @@
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/* Copyright (C) 2012 Free Software Foundation, Inc.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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|
FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "asmcfi.h"
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#ifdef __arch64__
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# define WORD_SIZE 8
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# define MIN_FRAME_SIZE 176
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# define STACK_BIAS 2047
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# define load ldx
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# define store stx
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#else
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# define WORD_SIZE 4
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# define MIN_FRAME_SIZE 96
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# define STACK_BIAS 0
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# define load ld
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# define store st
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#endif
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/* Fields of the JmpBuf structure. */
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#define JB_CFA 0
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#define JB_PC 1
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#define OFFSET(FIELD) ((FIELD) * WORD_SIZE)
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/* The frame size must be a multiple of the double-word size. */
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#define FRAME_SIZE (MIN_FRAME_SIZE + 2 * WORD_SIZE)
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#define JB_OFFSET (STACK_BIAS + MIN_FRAME_SIZE)
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.text
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.align 4
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.globl _ITM_beginTransaction
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.type _ITM_beginTransaction, #function
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.proc 016
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_ITM_beginTransaction:
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cfi_startproc
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add %sp, STACK_BIAS, %g1
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sub %sp, FRAME_SIZE, %sp
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cfi_def_cfa_offset(STACK_BIAS + FRAME_SIZE)
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store %g1, [%sp + JB_OFFSET + OFFSET (JB_CFA)]
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store %o7, [%sp + JB_OFFSET + OFFSET (JB_PC)]
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/* ??? This triggers an internal error in GDB. */
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cfi_offset(%o7, -WORD_SIZE)
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call GTM_begin_transaction
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add %sp, JB_OFFSET, %o1
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load [%sp + JB_OFFSET + OFFSET (JB_PC)], %o7
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jmp %o7+8
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add %sp, FRAME_SIZE, %sp
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cfi_def_cfa_offset(STACK_BIAS)
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cfi_endproc
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.size _ITM_beginTransaction, . - _ITM_beginTransaction
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.align 4
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.globl GTM_longjmp
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#ifdef HAVE_ATTRIBUTE_VISIBILITY
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.hidden GTM_longjmp
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#endif
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.type GTM_longjmp, #function
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.proc 016
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GTM_longjmp:
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cfi_startproc
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flushw
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load [%o1 + OFFSET (JB_CFA)], %fp
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cfi_def_cfa(%fp, 0)
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#if STACK_BIAS
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sub %fp, STACK_BIAS, %fp
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cfi_def_cfa_offset(STACK_BIAS)
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#endif
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load [%o1 + OFFSET (JB_PC)], %o7
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jmp %o7+8
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restore %g0, %o0, %o0
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cfi_endproc
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.size GTM_longjmp, . - GTM_longjmp
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#ifdef __linux__
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.section .note.GNU-stack, "", @progbits
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#endif
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@ -0,0 +1,46 @@
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/* Copyright (C) 2012 Free Software Foundation, Inc.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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|
permissions described in the GCC Runtime Library Exception, version
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|
3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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namespace GTM HIDDEN {
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typedef struct gtm_jmpbuf
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{
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void *cfa;
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unsigned long pc;
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} gtm_jmpbuf;
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/* UltraSPARC processors generally use a fixed page size of 8K. */
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#define PAGE_SIZE 8192
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#define FIXED_PAGE_SIZE 1
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/* The size of one line in hardware caches (in bytes). We use the primary
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cache line size documented for the UltraSPARC T1/T2. */
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#define HW_CACHELINE_SIZE 16
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static inline void
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cpu_relax (void)
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{
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__asm volatile ("" : : : "memory");
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}
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} // namespace GTM
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@ -66,6 +66,34 @@ case "${target_cpu}" in
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sh*) ARCH=sh ;;
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sh*) ARCH=sh ;;
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sparc)
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case " ${CC} ${CFLAGS} " in
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*" -m64 "*)
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;;
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*)
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if test -z "$with_cpu"; then
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XCFLAGS="${XCFLAGS} -mcpu=v9"
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fi
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esac
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ARCH=sparc
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;;
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sparc64|sparcv9)
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case " ${CC} ${CFLAGS} " in
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*" -m32 "*)
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XCFLAGS="${XCFLAGS} -mcpu=v9"
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;;
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*" -m64 "*)
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;;
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*)
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if test "x$with_cpu" = xv8; then
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XCFLAGS="${XCFLAGS} -mcpu=v9"
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fi
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;;
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esac
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ARCH=sparc
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;;
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x86_64)
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x86_64)
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case " ${CC} ${CFLAGS} " in
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case " ${CC} ${CFLAGS} " in
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*" -m32 "*)
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*" -m32 "*)
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Loading…
Reference in New Issue